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Thu, 29 Aug 2024 23:41:55 -0700 (PDT) Received: from kylee-ThinkPad-E16-Gen-1 ([122.147.171.160]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2051556a712sm20796435ad.307.2024.08.29.23.41.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2024 23:41:55 -0700 (PDT) Date: Fri, 30 Aug 2024 14:41:49 +0800 From: Kuan-Ying Lee To: lijiang Cc: Baoquan He , Will Deacon , HAGIO =?utf-8?B?S0FaVUhJVE8o6JCp5bC+IOS4gOS7gSk=?= , Vivek Goyal , Dave Young , Jonathan Corbet , Catalin Marinas , kexec@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ardb@kernel.org Subject: Re: [PATCH] arm64/vmcore: Add pgtable_l5_enabled information in vmcoreinfo Message-ID: References: <20240826065219.305963-1-kuan-ying.lee@canonical.com> <20240827122459.GA4679@willie-the-truck> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, Aug 28, 2024 at 05:37:07PM +0800, lijiang wrote: > On Wed, Aug 28, 2024 at 6:48 AM Baoquan He wrote: > > > On 08/27/24 at 01:24pm, Will Deacon wrote: > > > On Mon, Aug 26, 2024 at 02:52:02PM +0800, Kuan-Ying Lee wrote: > > > > Since arm64 supports 5-level page tables, we need to add this > > > > information to vmcoreinfo to make debug tools know if 5-level > > > > page table is enabled or not. > > > > > > > > Missing this information will break the debug tool like crash [1]. Sorry, the above line was mistakenly expressed. Currently, the crash tool doesn't support 4K page with 5-level page tables (LPA2), so I initially planned to add this information to implement support for 4K page with 5-level page table in the crash tool. > > > > > > > > [1] https://github.com/crash-utility/crash > > > > > > > > Signed-off-by: Kuan-Ying Lee > > > > --- > > > > Documentation/admin-guide/kdump/vmcoreinfo.rst | 6 ++++++ > > > > arch/arm64/kernel/vmcore_info.c | 3 +++ > > > > 2 files changed, 9 insertions(+) > > > > > > In which case, wouldn't you also want to know about pgtable_l4_enabled()? > > > > That is a good question. I guess it's deduced in code, mostly needed for > > different PAGE_OFFSET, how to transfer virtual addr to physical addr, > > etc. > > > > > Thanks for the information, Baoquan. > > If I understand correctly, for arm64, currently, the crash tool determines > the levels of the page table based on page size and va_bits, and then > decides how to translate the address, such as calculating it in conjunction > with other values, e.g: kernel pgd, offset, etc. Thanks for the information. I will then try to use VA_BITS to determine if it is a 5-level page table. Let me investigate further. Thanks, Kuan-Ying Lee > > For more details, please refer to this one: > https://github.com/crash-utility/crash/blob/master/arm64.c > > > Thanks > Lianbo > > > > Add Crash utility experts here. > > > >