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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?gHKslOkqDxGl8r5dgdg7f0YQhJOZUCXKHGuR9gV2eawlleQSdvrSuRWugtx0?= =?us-ascii?Q?U0DnHVURxJgB27r04B6e2hzYtuRnpwMiLhFVBCkjX4ycouDJi807iY4ySmSW?= =?us-ascii?Q?qWgYjkG7ZL7Q5uKFCx5DId868FhGILY6T+xK4Oi4FY8QeSKO5vqT0FsjIozJ?= =?us-ascii?Q?81POtJTLZG9w4kE2uewf/ljZQAjdIH3n3IE6on491Xi2P3lsMMmz+ShmNdKB?= =?us-ascii?Q?jdDVtWHDZLoF76MrWfYYISyKLk7QTG6sEdJsdyqTWfYIxfHDwkQzYAa6FtS7?= =?us-ascii?Q?7WBrReH8eEK7VUV5znufg/LS+pOAuQaEeAR2+oa+O8E6w195uRSRQvRqqrXY?= =?us-ascii?Q?kVEwjPEZmB30CHcz3BkaWSt1dVxpbmTTeJMJJsxkbfAggyZMA5kqox0cPbqK?= =?us-ascii?Q?/KlLEpnHBT2a6V5BEQ8NQzm4A0n1PCta6RpnDnU5iu2qkN9fNE5SpuM/MdEq?= =?us-ascii?Q?O06O0/WoYAYFsloLf4OLQatZv59Df8q1EgdYOeKcCjs+iVZpwf/khGPHghNm?= =?us-ascii?Q?T7k0gn6D+pbmbhIp5YQKrGMCAUIQDw0PaRjOordhec8BH2+CNA+9Pg1i/6Ze?= =?us-ascii?Q?opmZYW+WiC/T8NSUAF2om3hWePn5qFI/8i5xxAcoHldLD80jClDkVMEwJGzZ?= =?us-ascii?Q?9/8Y2KIt/FeVzRaPLtCPit/MGR6HWV/2G3HjEE0Wji+ESsNT+YeFRYrlaX0U?= =?us-ascii?Q?SAmqacpheBn4hjkqiyFd1+4beNQY4S7dA+RykUJFbEa3M1ile4pFdGqh8ozY?= =?us-ascii?Q?K0hqgzJzrlAgt/juLGpkL3ojqVB37jAx/6CdxkFNqr578xXg3iCt9Rl67cFW?= =?us-ascii?Q?K86bqAT1No1TkKq/ANbO5NhfJcQzw00GU8hYOkoiCxolr8timsDAZL3vd3zB?= =?us-ascii?Q?2GpAVJMdRsefqFPG8ih1SMzHrLLxZh40ginSx16TpsSrOoxLgKDaeSO/EB9R?= =?us-ascii?Q?1aKW1TiLfInINH55ZrE4psyzC25qp+rFSTlM2z1mJWe+sqCPUZ4OcNkJs73a?= =?us-ascii?Q?DRmPyqMpFMgR/IAtgP550O3UYgN0e0TRW+Zz9SYyb4DD52IONVUv2hMiJx7s?= =?us-ascii?Q?BORcA25taCL+L1fE4wBIbW6WdG5TWzSEW0SpJiNvlkyd0V9eiYTwHLhK8xwX?= =?us-ascii?Q?1q5yMyZJ/M326WR8upJ1fgcG98BonJgK2iC4VGQhBXefCcZD3iFGSijWAleG?= =?us-ascii?Q?V9UCdVIrabRrl6A9h/TRb2PDkNzxfh/juL+8XflsKC+VnnTBfUD2GvfcSls0?= =?us-ascii?Q?g22bgQIx61YF1W/O8ZFFW3ZrZZRzBKbxdwnLugk28MCIWf2kpe0Xo+b33mg0?= =?us-ascii?Q?K183hGald94wWAuKCG8kTCBKBC6rGcuP2dF8Dx/+XzDdlcogx9J2lfZPNXXY?= =?us-ascii?Q?WEgEGGTUvEE8lFr8dJiYD6y0KmygwsNwTxCADknjhTgPdthlIVfq7G6OPCB+?= =?us-ascii?Q?22nCiKwwBJHhIpid6uJ69cqhOKF3cs3kCjwIasTEW/bidxi/hu0EqQrixNZ0?= =?us-ascii?Q?cwDGGzjKTCr3oomfHsqtU1q8Yw62ci0gjuUovpnccyErV61rTP+4qm+K7iCs?= =?us-ascii?Q?5eT5pMPlQQ4GXCcR+eTB8lmKIfgozyk8nW3qxLob?= X-MS-Exchange-CrossTenant-Network-Message-Id: f40a90eb-0965-479e-3eca-08dce06992db X-MS-Exchange-CrossTenant-AuthSource: DS7PR11MB5966.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2024 09:32:02.0629 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mDtTSzYLJUyVX1rCvfnDj6nl+koVf5jd1iagqCdi7TTsxIAn7p2fe9UpADiUJ2hQaOJQL+teFRfmzi+0/w6RZQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR11MB7578 X-OriginatorOrg: intel.com On Fri, Sep 27, 2024 at 06:51:58AM -0700, Sean Christopherson wrote: > On Thu, Sep 26, 2024, Yan Zhao wrote: > > On Thu, Sep 12, 2024 at 05:07:57PM -0700, Sean Christopherson wrote: > > > > diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h > > > > index a72f0e3bde17..1726f8ec5a50 100644 > > > > --- a/arch/x86/kvm/mmu/spte.h > > > > +++ b/arch/x86/kvm/mmu/spte.h > > > > @@ -214,6 +214,12 @@ extern u64 __read_mostly shadow_nonpresent_or_rsvd_mask; > > > > */ > > > > #define FROZEN_SPTE (SHADOW_NONPRESENT_VALUE | 0x5a0ULL) > > > > > > > > +#define EXTERNAL_SPTE_IGNORE_CHANGE_MASK \ > > > > + (shadow_acc_track_mask | \ > > > > + (SHADOW_ACC_TRACK_SAVED_BITS_MASK << \ > > > > + SHADOW_ACC_TRACK_SAVED_BITS_SHIFT) | \ > > > > > > Just make TDX require A/D bits, there's no reason to care about access tracking. > > If KVM_PRE_FAULT_MEMORY is allowed for TDX and if > > cpu_has_vmx_ept_ad_bits() is false in TDX's hardware (not sure if it's possible), > > Make it a requirement in KVM that TDX hardware supports A/D bits and that KVM's > module param is enabled. EPT A/D bits have been supported in all CPUs since > Haswell, I don't expect them to ever go away. Got it! > > > access tracking bit is possbile to be changed, as in below scenario: > > > > 1. KVM_PRE_FAULT_MEMORY ioctl calls kvm_arch_vcpu_pre_fault_memory() to map > > a GFN, and make_spte() will call mark_spte_for_access_track() to > > remove shadow_acc_track_mask (i.e. RWX bits) and move R+X left to > > SHADOW_ACC_TRACK_SAVED_BITS_SHIFT. > > 2. If a concurrent page fault occurs on the same GFN on another vCPU, then > > make_spte() in that vCPU will not see prefetch and the new_spte is > > with RWX bits and with no bits set in SHADOW_ACC_TRACK_SAVED_MASK. > > This should be fixed by the mega-series. I'll make sure to Cc you on that series. Thanks! > Thanks much for the input and feedback! :)