From: Andrea Parri <parri.andrea@gmail.com>
To: Davidlohr Bueso <dave@stgolabs.net>
Cc: palmer@dabbelt.com, jimw@sifive.com, guoren@kernel.org,
dlustig@nvidia.com, boqun.feng@gmail.com, peterz@infradead.org,
will@kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] riscv/futex: Optimize atomic cmpxchg
Date: Wed, 13 Nov 2024 21:15:05 +0200 [thread overview]
Message-ID: <ZzT6uRDpkuEu5GH-@andrea> (raw)
In-Reply-To: <20241113183321.491113-1-dave@stgolabs.net>
On Wed, Nov 13, 2024 at 10:33:21AM -0800, Davidlohr Bueso wrote:
> Remove redundant release/acquire barriers, optimizing the lr/sc sequence
> to provide conditional RCsc synchronization, per the RVWMO.
>
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
> ---
> arch/riscv/include/asm/futex.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/futex.h b/arch/riscv/include/asm/futex.h
> index fc8130f995c1..72be100afa23 100644
> --- a/arch/riscv/include/asm/futex.h
> +++ b/arch/riscv/include/asm/futex.h
> @@ -85,7 +85,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
>
> __enable_user_access();
> __asm__ __volatile__ (
> - "1: lr.w.aqrl %[v],%[u] \n"
> + "1: lr.w %[v],%[u] \n"
> " bne %[v],%z[ov],3f \n"
> "2: sc.w.aqrl %[t],%z[nv],%[u] \n"
> " bnez %[t],1b \n"
atomic_cmpxchg() uses yet another scheme, but this does also look good
to me: FWIW,
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
Andrea
next parent reply other threads:[~2024-11-13 19:15 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20241113183321.491113-1-dave@stgolabs.net>
2024-11-13 19:15 ` Andrea Parri [this message]
2025-01-30 14:10 ` patchwork-bot+linux-riscv
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