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Thu, 14 Nov 2024 20:04:21 -0800 (PST) Received: from archie.me ([103.124.138.80]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7f8c1dade0esm399915a12.66.2024.11.14.20.04.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 20:04:19 -0800 (PST) Received: by archie.me (Postfix, from userid 1000) id E5F9644D87F4; Fri, 15 Nov 2024 11:04:15 +0700 (WIB) Date: Fri, 15 Nov 2024 11:04:15 +0700 From: Bagas Sanjaya To: Even Xu , jikos@kernel.org, bentiss@kernel.org, corbet@lwn.net, aaron.ma@canonical.com Cc: linux-input@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Sun Xinpeng , Srinivas Pandruvada Subject: Re: [PATCH v2 01/22] HID: THC: Add documentation Message-ID: References: <20241114053416.4085715-1-even.xu@intel.com> <20241114053416.4085715-2-even.xu@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="piiGGXBvEqKZuoLP" Content-Disposition: inline In-Reply-To: <20241114053416.4085715-2-even.xu@intel.com> --piiGGXBvEqKZuoLP Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Nov 14, 2024 at 01:33:55PM +0800, Even Xu wrote: > +Touch Host Controller is the name of the IP block in PCH that interface = with Touch Devices (ex: > +touchscreen, touchpad etc.). It is comprised of 3 key functional blocks: > +- A natively half-duplex Quad I/O capable SPI master > +- Low latency I2C interface to support HIDI2C compliant devices > +- A HW sequencer with RW DMA capability to system memory I see in my htmldocs output that the list above is long running paragraph instead. > +When THC is configured to SPI mode, opcodes are used for determining the= read/write IO mode. > +There are some OPCode examples for SPI IO mode:: > + > + +--------+---------------------------------+ > + | opcode | Corresponding SPI command | > + +=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ > + | 0x0B | Read Single I/O | > + +--------+---------------------------------+ > + | 0x02 | Write Single I/O | > + +--------+---------------------------------+ > + | 0xBB | Read Dual I/O | > + +--------+---------------------------------+ > + | 0xB2 | Write Dual I/O | > + +--------+---------------------------------+ > + | 0xEB | Read Quad I/O | > + +--------+---------------------------------+ > + | 0xE2 | Write Quad I/O | > + +--------+---------------------------------+ > + > ... > +When THC is working in I2C mode, opcodes are used to tell THC what's the= next PIO type: > +I2C SubIP APB register read, I2C SubIP APB register write, I2C touch IC = device read, > +I2C touch IC device write, I2C touch IC device write followed by read. > + > +Here are the THC pre-defined opcodes for I2C mode:: > + > + +--------+-------------------------------------------+----------+ > + | opcode | Corresponding I2C command | Address | > + +=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ > + | 0x12 | Read I2C SubIP APB internal registers | 0h - FFh | > + +--------+-------------------------------------------+----------+ > + | 0x13 | Write I2C SubIP APB internal registers | 0h - FFh | > + +--------+-------------------------------------------+----------+ > + | 0x14 | Read external Touch IC through I2C bus | N/A | > + +--------+-------------------------------------------+----------+ > + | 0x18 | Write external Touch IC through I2C bus | N/A | > + +--------+-------------------------------------------+----------+ > + | 0x1C | Write then read external Touch IC through | N/A | > + | | I2C bus | | > + +--------+-------------------------------------------+----------+ > + > ... > +Intel THC uses PRD entry descriptor for every PRD entry. Every PRD entry= descriptor occupies > +128 bits memories:: > + > + +-------------------+---------+----------------------------------------= --------+ > + | struct field | bit(s) | description = | > + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D= =3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D+ > + | dest_addr | 53..0 | destination memory address, as every en= try | > + | | | is 4KB, ignore lowest 10 bits of addres= s. | > + +-------------------+---------+----------------------------------------= --------+ > + | reserved1 | 54..62 | reserved = | > + +-------------------+---------+----------------------------------------= --------+ > + | int_on_completion | 63 | completion interrupt enable bit, if thi= s bit | > + | | | set it means THC will trigger a complet= ion | > + | | | interrupt. This bit is set by SW driver= =2E | > + +-------------------+---------+----------------------------------------= --------+ > + | len | 87..64 | how many bytes of data in this entry. = | > + +-------------------+---------+----------------------------------------= --------+ > + | end_of_prd | 88 | end of PRD table bit, if this bit is se= t, | > + | | | it means this entry is last entry in th= is PRD | > + | | | table. This bit is set by SW driver. = | > + +-------------------+---------+----------------------------------------= --------+ > + | hw_status | 90..89 | HW status bits = | > + +-------------------+---------+----------------------------------------= --------+ > + | reserved2 | 127..91 | reserved = | > + +-------------------+---------+----------------------------------------= --------+ Shouldn't these tables be formatted as tables? Thanks. --=20 An old man doll... just what I always wanted! - Clara --piiGGXBvEqKZuoLP Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQSSYQ6Cy7oyFNCHrUH2uYlJVVFOowUCZzbIOgAKCRD2uYlJVVFO oz6LAP99VEDsehlAPR+X9zgwEkcCE1Mko2zX3n4bSOBlpayWiAEA/hRSe5+cRDaQ lkGYtBq5mXgsRyz54qqxWBPELSNZNA0= =thPG -----END PGP SIGNATURE----- --piiGGXBvEqKZuoLP--