Re: platform/x86: p2sb: Allow p2sb_bar() calls during PCI device probe

["Daniel Walker (danielwa)" <danielwa@cisco.com>]

On Mon, Nov 18, 2024 at 03:49:32PM +0200, Andy Shevchenko wrote:
> On Mon, Nov 18, 2024 at 01:32:55PM +0000, Daniel Walker (danielwa) wrote:
> > On Mon, Nov 18, 2024 at 03:24:20PM +0200, Andy Shevchenko wrote:
> > > On Mon, Nov 18, 2024 at 12:40:16PM +0000, Daniel Walker (danielwa) wrote:
> 
> ...
> 
> > > Are you referring to LPC GPIO?
> >  
> >  I don't know the hardware well enough to say for certain. It's whatever device 8086:19dd is.
> 
> This is device which represents p2sb. It's not a GPIO device you are talking
> about for sure. You can send privately more detailed info in case this is shouldn't
> be on public to me to understand what would be the best approach to fix your issue.

Here's a comment,

/* INTEL Denverton GPIO registers are accessible using SBREG_BAR(bar 0) as base */

We have gpio wired to an FPGA and I believe the gpio line is used to reset the
fpga.

So the pci resources attached to 8086:19dd can be used to access gpio of some
type. 

I'm not a pci expert but on the 19bb device bar 0 we use the below offset to manipulate
the gpio,

#define INTEL_GPIO_REG_RESET_OFFSET          0xC50578

The comments suggest this is gpio 6. I would seems your reaction would be that
there is no gpio on the 19dd device. Maybe our driver is access gpio thru p2sb
or something like that.

Does the offset above make sense to you in the context of the p2sb ?

Daniel