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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f1966471dsm17467943b3a.6.2026.05.19.01.26.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 May 2026 01:26:27 -0700 (PDT) Message-ID: Date: Tue, 19 May 2026 16:26:21 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 13/39] drm/msm/dp: introduce stream_id for each DP panel To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> <20260410-msm-dp-mst-v4-13-b20518dea8de@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=F9ZnsKhN c=1 sm=1 tr=0 ts=6a0c1eb4 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=5QDKDTwAGq_DmF9AEKQA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 7QUNC52fagbYpFzfA5ySbs7F0Y6QXhDD X-Proofpoint-GUID: 7QUNC52fagbYpFzfA5ySbs7F0Y6QXhDD X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA4MyBTYWx0ZWRfXxAvkENzaqvV7 bP/XyPIyfLuFOeK5RbMuQ3cf568hGmx6EQtfWZ24nWOYa+4gVdvHQNhl2v8bOfeQSSjyMxDmLUY eh+86x6HR3pmwXUdNhjlaafS5ShhRimPGQBoLH+Nh76ElHlwrfqVWvMVRGhewjwajBLbftO9B7v r4ogEl4rE57pyWa09RYp+CxrpJZFrTn0s+pxdgHRK89sh6nlSE/jZxUJ6jMmNp9lE+GavqdnCCQ Mp7tH4VziBuUW8V3yrLypl4zgVtUVhJBAz81A+3Az0GCcm+ZsoFUO076RWKAcPz5vmKG9JXs8FD aru84CXSJ7CrH6jlCHUIVn8gUg5MqIXiVkTvliavTTZpwkm4bTlonhMr5nsYhZrbA32GdPjLhyl 6GYcebF6wH4ehTSkDQW+cTRsi5HeSCB/llpg75fJXqip4Cm+NAqnrrlyBUcVuXbNWkuj3Ap8X6K lcmuqanVrPUhT5Ry9Kw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 suspectscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190083 On 4/12/2026 1:55 AM, Dmitry Baryshkov wrote: > On Fri, Apr 10, 2026 at 05:33:48PM +0800, Yongxing Mou wrote: >> From: Abhinav Kumar >> >> With MST, each DP controller can handle multiple streams. >> There shall be one dp_panel for each stream but the dp_display >> object shall be shared among them. To represent this abstraction, >> create a stream_id for each DP panel which shall be set by the >> MST stream. For SST, default this to stream 0. >> >> Use the stream ID to control the pixel clock of that respective >> stream by extending the clock handles and state tracking of the >> DP pixel clock to an array of max supported streams. The maximum >> streams currently is 4. > > Please mention that panels are going to be dynamically assigned to > actual stream IDs. > Got it. will update next patch. >> >> Signed-off-by: Abhinav Kumar >> Signed-off-by: Yongxing Mou >> --- >> drivers/gpu/drm/msm/dp/dp_ctrl.c | 57 +++++++++++++++++++++++-------------- >> drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- >> drivers/gpu/drm/msm/dp/dp_display.c | 24 ++++++++++++++-- >> drivers/gpu/drm/msm/dp/dp_display.h | 2 ++ >> drivers/gpu/drm/msm/dp/dp_panel.h | 11 +++++++ >> 5 files changed, 71 insertions(+), 25 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c >> index 120ec00884e5..fb6396727628 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c >> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c >> @@ -127,7 +127,7 @@ struct msm_dp_ctrl_private { >> unsigned int num_link_clks; >> struct clk_bulk_data *link_clks; >> >> - struct clk *pixel_clk; >> + struct clk *pixel_clk[DP_STREAM_MAX]; >> >> union phy_configure_opts phy_opts; >> >> @@ -139,7 +139,7 @@ struct msm_dp_ctrl_private { >> >> bool core_clks_on; >> bool link_clks_on; >> - bool stream_clks_on; >> + bool stream_clks_on[DP_STREAM_MAX]; >> }; >> >> static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, u32 offset) >> @@ -2176,39 +2176,40 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl) >> return success; >> } >> >> -static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate) >> +static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate, >> + enum msm_dp_stream_id stream_id) >> { >> int ret; >> >> - ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); >> + ret = clk_set_rate(ctrl->pixel_clk[stream_id], pixel_rate * 1000); >> if (ret) { >> DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); >> return ret; >> } >> >> - if (ctrl->stream_clks_on) { >> + if (ctrl->stream_clks_on[stream_id]) { >> drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); >> } else { >> - ret = clk_prepare_enable(ctrl->pixel_clk); >> + ret = clk_prepare_enable(ctrl->pixel_clk[stream_id]); >> if (ret) { >> DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); >> return ret; >> } >> - ctrl->stream_clks_on = true; >> + ctrl->stream_clks_on[stream_id] = true; >> } >> >> return ret; >> } >> >> -void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) >> +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_dp_stream_id stream_id) >> { >> struct msm_dp_ctrl_private *ctrl; >> >> ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); >> >> - if (ctrl->stream_clks_on) { >> - clk_disable_unprepare(ctrl->pixel_clk); >> - ctrl->stream_clks_on = false; >> + if (ctrl->stream_clks_on[stream_id]) { >> + clk_disable_unprepare(ctrl->pixel_clk[stream_id]); >> + ctrl->stream_clks_on[stream_id] = false; >> } >> } >> >> @@ -2228,7 +2229,7 @@ static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl >> * running. Add the global reset just before disabling the >> * link clocks and core clocks. >> */ >> - msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl); >> + msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl, ctrl->panel->stream_id); > > Why are we using ctrl->panel again here for the stream-related > functions? Didn't you got rid of its usage few patches ago? > For MST path, we pass panel to the func. For SST case, we still need to pass the sst panel to func, in here it is ctrl->panel.. in dp_display, it is dp_display->panel. >> msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl); >> >> ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); >> @@ -2238,7 +2239,7 @@ static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl >> } >> >> pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; >> - ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); >> + ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, ctrl->panel->stream_id); > > And here... > >> >> msm_dp_ctrl_send_phy_test_pattern(ctrl); >> >> @@ -1451,6 +1469,8 @@ void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) >> >> dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); >> >> + msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0); > > DP_STREAM_0 > >> + >> rc = msm_dp_display_enable(dp); >> if (rc) >> DRM_ERROR("DP display enable failed, rc=%d\n", rc); >