From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751020AbdL0Gks (ORCPT ); Wed, 27 Dec 2017 01:40:48 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:60817 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750762AbdL0Gkq (ORCPT ); Wed, 27 Dec 2017 01:40:46 -0500 Subject: Re: [PATCH v2 2/3] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7 To: Tony Lindgren , Rob Herring References: <20171219085823.8695-1-kishon@ti.com> <20171219085823.8695-3-kishon@ti.com> <20171220185715.j5h7dlricom6kuiz@rob-hp-laptop> <94336bfb-221d-95f7-72b2-09219b08099b@ti.com> <20171222182448.GZ3875@atomide.com> <20171226181009.GE3875@atomide.com> CC: Lorenzo Pieralisi , Bjorn Helgaas , Mark Rutland , linux-omap , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , , "linux-kernel@vger.kernel.org" , Sekhar Nori From: Kishon Vijay Abraham I Message-ID: Date: Wed, 27 Dec 2017 12:10:32 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.0 MIME-Version: 1.0 In-Reply-To: <20171226181009.GE3875@atomide.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Tuesday 26 December 2017 11:40 PM, Tony Lindgren wrote: > * Rob Herring [171226 17:49]: >> On Fri, Dec 22, 2017 at 12:24 PM, Tony Lindgren wrote: >>> * Kishon Vijay Abraham I [171222 06:06]: >>>> Hi Rob, >>>> >>>> On Thursday 21 December 2017 12:27 AM, Rob Herring wrote: >>>>> On Tue, Dec 19, 2017 at 02:28:22PM +0530, Kishon Vijay Abraham I wrote: >>>>>> Add syscon properties required for configuring PCIe in x2 lane mode. >>>>>> >>>>>> Signed-off-by: Kishon Vijay Abraham I >>>>>> Signed-off-by: Sekhar Nori >>>>>> --- >>>>>> Documentation/devicetree/bindings/pci/ti-pci.txt | 6 ++++++ >>>>>> 1 file changed, 6 insertions(+) >>>>>> >>>>>> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt >>>>>> index 82cb875e4cec..bfbc77ac7355 100644 >>>>>> --- a/Documentation/devicetree/bindings/pci/ti-pci.txt >>>>>> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt >>>>>> @@ -13,6 +13,12 @@ PCIe DesignWare Controller >>>>>> - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", >>>>>> where is the instance number of the pcie from the HW spec. >>>>>> - num-lanes as specified in ../designware-pcie.txt >>>>>> + - ti,syscon-lane-conf : phandle/offset pair. Phandle to the system control >>>>>> + module and the register offset to specify 1 lane or >>>>>> + 2 lane. >>>>>> + - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control >>>>>> + module and the register offset to specify lane >>>>>> + selection. >>>>> >>>>> Adding a property for every syscon register doesn't really scale and >>>>> doesn't work if the register layout changes. >>>> >>>> The register layout doesn't really change between silicon revisions and for new >>>> SoCs, the phandle and the register offset for that SoC will have to be >>>> populated again. >> >> And what about SoCs that don't exist yet? >> >>>> Having said that, I'm not aware of any other alternative here. >> >> What would you do if you had 20 different syscon registers to >> configure? Add 20 properties? No, you would have per SoC functions in >> the driver to handle the different cases. > > Ideally these syscon registers would be managed by some Linux > generic framework such as clock/regulator/mux/phy. > > But yeah, if that does not work, then setting a SoC specific > configuration function based on the compatible value makes sense > to me. All right. I'll add a function for syscon configuration in pci-dra7xx. Thanks Kishon