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Mon, 24 Feb 2025 06:37:44 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51O6bU8e018152 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Feb 2025 06:37:30 GMT Received: from [10.217.216.47] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 23 Feb 2025 22:37:24 -0800 Message-ID: Date: Mon, 24 Feb 2025 12:07:21 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] clk: qcom: videocc: Add support to attach multiple power domains To: Konrad Dybcio , Bryan O'Donoghue , Bjorn Andersson , "Michael Turquette" , Stephen Boyd , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Konrad Dybcio CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , References: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> <20250218-videocc-pll-multi-pd-voting-v1-4-cfe6289ea29b@quicinc.com> <1d9b661e-0607-4567-b420-5444b643df99@oss.qualcomm.com> Content-Language: en-US From: Jagadeesh Kona In-Reply-To: <1d9b661e-0607-4567-b420-5444b643df99@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ZezeoRbAm_q98-sJTHR6RnYGE54XLHXz X-Proofpoint-GUID: ZezeoRbAm_q98-sJTHR6RnYGE54XLHXz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-24_02,2025-02-20_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 bulkscore=0 spamscore=0 phishscore=0 clxscore=1015 impostorscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502240047 On 2/22/2025 12:49 AM, Konrad Dybcio wrote: > On 18.02.2025 4:46 PM, Bryan O'Donoghue wrote: >> On 18/02/2025 14:26, Jagadeesh Kona wrote: >>> During boot-up, the PLL configuration might be missed even after >>> calling pll_configure() from the clock controller probe. This can >>> happen because the PLL is connected to one or more rails that are >>> turned off, and the current clock controller code cannot enable >>> multiple rails during probe. Consequently, the PLL may be activated >>> with suboptimal settings, causing functional issues. >>> >>> To properly configure the video PLLs in the probe on SM8450, SM8475, >>> SM8550, and SM8650 platforms, the MXC rail must be ON along with MMCX. >>> Therefore, add support to attach multiple power domains to videocc on >>> these platforms. >>> >>> Signed-off-by: Jagadeesh Kona >>> --- >>>   drivers/clk/qcom/videocc-sm8450.c | 4 ++++ >>>   drivers/clk/qcom/videocc-sm8550.c | 4 ++++ >>>   2 files changed, 8 insertions(+) >>> >>> diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c >>> index f26c7eccb62e7eb8dbd022e2f01fa496eb570b3f..b50a14547336580de88a741f1d33b126e9daa848 100644 >>> --- a/drivers/clk/qcom/videocc-sm8450.c >>> +++ b/drivers/clk/qcom/videocc-sm8450.c >>> @@ -437,6 +437,10 @@ static int video_cc_sm8450_probe(struct platform_device *pdev) >>>       struct regmap *regmap; >>>       int ret; >>>   +    ret = qcom_cc_attach_pds(&pdev->dev, &video_cc_sm8450_desc); >>> +    if (ret) >>> +        return ret; >>> + >>>       ret = devm_pm_runtime_enable(&pdev->dev); >>>       if (ret) >>>           return ret; >>> diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c >>> index 7c25a50cfa970dff55d701cb24bc3aa5924ca12d..d4b223d1392f0721afd1b582ed35d5061294079e 100644 >>> --- a/drivers/clk/qcom/videocc-sm8550.c >>> +++ b/drivers/clk/qcom/videocc-sm8550.c >>> @@ -542,6 +542,10 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) >>>       int ret; >>>       u32 sleep_clk_offset = 0x8140; >>>   +    ret = qcom_cc_attach_pds(&pdev->dev, &video_cc_sm8550_desc); >>> +    if (ret) >>> +        return ret; >>> + >>>       ret = devm_pm_runtime_enable(&pdev->dev); >>>       if (ret) >>>           return ret; >>> >> >> What's the difference between doing the attach here or doing it in really_probe() ? >> >> There doesn't seem to be any difference except that we will have an additional delay introduced. >> >> Are you describing a race condition ? >> >> I don't see _logic_ here to moving the call into the controller's higher level probe. >> >> Can you describe some more ? > > I think this is a sane course of action: > > 1. associate pll config with the pll (treewide change) > 2. add a generic pll_configure call that parses the type > 3. store PLLs to be configured in an array of dt-bindings indices > 4. move PLL configuration to really_probe > 5. move RPM enablement to really_probe, make it conditional to limit resource > waste on e.g. gcc > 6. move attaching GDSCs to really_probe > > Konrad Thanks Konrad for your feedback and suggestion. I will check and work on this approach of moving PLL configure and RPM enablement to a common code. Thanks, Jagadeesh