From: Atish Patra <atish.patra@wdc.com>
To: Daniel Lezcano <daniel.lezcano@linaro.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>
Cc: Alan Kao <alankao@andestech.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Andreas Schwab <schwab@suse.de>, Anup Patel <anup@brainfault.org>,
Dmitriy Cherkasov <dmitriy@oss-tech.org>,
Guenter Roeck <linux@roeck-us.net>,
Jason Cooper <jason@lakedaemon.net>,
Johan Hovold <johan@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Marc Zyngier <marc.zyngier@arm.com>,
Palmer Dabbelt <palmer@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [v5 PATCH 6/8] clocksource/drivers/riscv: Add required checks during clock source init
Date: Thu, 14 Feb 2019 10:21:05 -0800 [thread overview]
Message-ID: <a0917630-489c-3ca4-e965-5a4ef2e4c4ca@wdc.com> (raw)
In-Reply-To: <bf8f0535-26d4-843a-d89c-8ab235411b4c@linaro.org>
On 2/14/19 2:24 AM, Daniel Lezcano wrote:
> On 13/02/2019 21:18, Atish Patra wrote:
>> Currently, clocksource registration happens for an invalid cpu for
>> non-smp kernels. This lead to kernel panic as cpu hotplug registration
>> will fail for those cpus. Moreover, riscv_hartid_to_cpuid can return
>> errors now.
>>
>> Do not proceed if hartid or cpuid is invalid. Take this opprtunity to
>> print appropriate error strings for different failure cases.
>>
>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>
> Hi Atish,
>
> I applied this patch for 5.1 with the typo fixed and the reviewed-by tags.
>
> -- Daniel
>
Thanks!!
Regards,
Atish
>> ---
>> drivers/clocksource/timer-riscv.c | 23 ++++++++++++++++++++---
>> 1 file changed, 20 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
>> index 43189220..e8163693 100644
>> --- a/drivers/clocksource/timer-riscv.c
>> +++ b/drivers/clocksource/timer-riscv.c
>> @@ -95,13 +95,30 @@ static int __init riscv_timer_init_dt(struct device_node *n)
>> struct clocksource *cs;
>>
>> hartid = riscv_of_processor_hartid(n);
>> + if (hartid < 0) {
>> + pr_warn("Not valid hartid for node [%pOF] error = [%d]\n",
>> + n, hartid);
>> + return hartid;
>> + }
>> +
>> cpuid = riscv_hartid_to_cpuid(hartid);
>> + if (cpuid < 0) {
>> + pr_warn("Invalid cpuid for hartid [%d]\n", hartid);
>> + return cpuid;
>> + }
>>
>> if (cpuid != smp_processor_id())
>> return 0;
>>
>> + pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
>> + __func__, cpuid, hartid);
>> cs = per_cpu_ptr(&riscv_clocksource, cpuid);
>> - clocksource_register_hz(cs, riscv_timebase);
>> + error = clocksource_register_hz(cs, riscv_timebase);
>> + if (error) {
>> + pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
>> + error, cpuid);
>> + return error;
>> + }
>>
>> sched_clock_register(riscv_sched_clock,
>> BITS_PER_LONG, riscv_timebase);
>> @@ -110,8 +127,8 @@ static int __init riscv_timer_init_dt(struct device_node *n)
>> "clockevents/riscv/timer:starting",
>> riscv_timer_starting_cpu, riscv_timer_dying_cpu);
>> if (error)
>> - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
>> - error, cpuid);
>> + pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
>> + error);
>> return error;
>> }
>>
>>
>
>
next prev parent reply other threads:[~2019-02-14 18:21 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-13 20:18 [v5 PATCH 0/8] Various SMP related fixes Atish Patra
2019-02-13 20:18 ` [v5 PATCH 1/8] RISC-V: Do not wait indefinitely in __cpu_up Atish Patra
2019-02-13 20:18 ` [v5 PATCH 2/8] RISC-V: Move cpuid to hartid mapping to SMP Atish Patra
2019-02-13 20:18 ` [v5 PATCH 3/8] RISC-V: Remove NR_CPUs check during hartid search from DT Atish Patra
2019-02-13 20:18 ` [v5 PATCH 4/8] RISC-V: Allow hartid-to-cpuid function to fail Atish Patra
2019-02-13 20:18 ` [v5 PATCH 5/8] RISC-V: Compare cpuid with NR_CPUS before mapping Atish Patra
2019-02-14 17:59 ` Christopher Lameter
2019-02-14 23:33 ` Atish Patra
2019-02-13 20:18 ` [v5 PATCH 6/8] clocksource/drivers/riscv: Add required checks during clock source init Atish Patra
2019-02-14 10:24 ` Daniel Lezcano
2019-02-14 18:21 ` Atish Patra [this message]
2019-02-13 20:18 ` [v5 PATCH 7/8] irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid Atish Patra
2019-02-13 20:18 ` [v5 PATCH 8/8] RISC-V: Assign hwcap as per comman capabilities Atish Patra
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