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Tue, 24 Sep 2024 07:36:13 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48O7aChu013627 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 24 Sep 2024 07:36:12 GMT Received: from [10.204.67.11] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 24 Sep 2024 00:36:03 -0700 Message-ID: Date: Tue, 24 Sep 2024 13:06:00 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/5] arm64: dts: qcom: sa8775p: add display dt nodes Content-Language: en-US To: Dmitry Baryshkov CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , References: <20240912071437.1708969-1-quic_mahap@quicinc.com> <20240912071437.1708969-6-quic_mahap@quicinc.com> From: Mahadevan P In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: jSNZQzWRDhpysE3fnS0fNyt0MRWttfnT X-Proofpoint-ORIG-GUID: jSNZQzWRDhpysE3fnS0fNyt0MRWttfnT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409240051 On 9/12/2024 1:30 PM, Dmitry Baryshkov wrote: > On Thu, Sep 12, 2024 at 12:44:37PM GMT, Mahadevan wrote: >> Add mdss and mdp DT nodes for SA8775P. >> >> Signed-off-by: Mahadevan >> --- >> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 85 +++++++++++++++++++++++++++ >> 1 file changed, 85 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> index 67ba124d20f8..d5d8e02fdb29 100644 >> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> @@ -6,6 +6,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -2937,6 +2938,90 @@ camcc: clock-controller@ade0000 { >> #power-domain-cells = <1>; >> }; >> >> + mdss0: display-subsystem@ae00000 { > Is there going to be mdss1? Currently we don't have plan to enable mdss1. Do we need to rename label to just "mdss" in that case? > >> + compatible = "qcom,sa8775p-mdss"; >> + reg = <0x0 0x0ae00000 0x0 0x1000>; >> + reg-names = "mdss"; >> + >> + /* same path used twice */ >> + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, >> + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY >> + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; >> + interconnect-names = "mdp0-mem", >> + "mdp1-mem", >> + "cpu-cfg"; >> + >> + power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; >> + >> + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, >> + <&gcc GCC_DISP_HF_AXI_CLK>, >> + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; >> + >> + interrupts = ; >> + interrupt-controller; >> + #interrupt-cells = <1>; >> + >> + iommus = <&apps_smmu 0x1000 0x402>; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + status = "disabled"; >> + >> + mdss0_mdp: display-controller@ae01000 { >> + compatible = "qcom,sa8775p-dpu"; >> + reg = <0x0 0x0ae01000 0x0 0x8f000>, >> + <0x0 0x0aeb0000 0x0 0x2008>; >> + reg-names = "mdp", "vbif"; >> + >> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, >> + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, >> + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, >> + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, >> + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; > Wrong indentation Sure will correct. > >> + clock-names = "bus", >> + "iface", >> + "lut", >> + "core", >> + "vsync"; >> + >> + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; >> + assigned-clock-rates = <19200000>; >> + >> + operating-points-v2 = <&mdss0_mdp_opp_table>; >> + power-domains = <&rpmhpd RPMHPD_MMCX>; >> + >> + interrupt-parent = <&mdss0>; >> + interrupts = <0>; >> + >> + mdss0_mdp_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-375000000 { >> + opp-hz = /bits/ 64 <375000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + }; >> + >> + opp-500000000 { >> + opp-hz = /bits/ 64 <500000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + >> + opp-575000000 { >> + opp-hz = /bits/ 64 <575000000>; >> + required-opps = <&rpmhpd_opp_turbo>; >> + }; >> + >> + opp-650000000 { >> + opp-hz = /bits/ 64 <650000000>; >> + required-opps = <&rpmhpd_opp_turbo_l1>; >> + }; >> + }; >> + }; >> + }; >> + >> dispcc0: clock-controller@af00000 { >> compatible = "qcom,sa8775p-dispcc0"; >> reg = <0x0 0x0af00000 0x0 0x20000>; >> -- >> 2.34.1 >>