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Wed, 17 Dec 2025 23:48:19 -0800 (PST) Message-ID: Date: Thu, 18 Dec 2025 09:48:18 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 6/6] dmaengine: sh: rz-dmac: Add device_{pause,resume}() callbacks To: vkoul@kernel.org, fabrizio.castro.jz@renesas.com, biju.das.jz@bp.renesas.com, geert+renesas@glider.be, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea References: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> <20251217135213.400280-7-claudiu.beznea.uj@bp.renesas.com> Content-Language: en-US From: Claudiu Beznea In-Reply-To: <20251217135213.400280-7-claudiu.beznea.uj@bp.renesas.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, On 12/17/25 15:52, Claudiu wrote: > From: Claudiu Beznea > > Add support for device_{pause, resume}() callbacks. These are required by > the RZ/G2L SCIFA driver. > > Signed-off-by: Claudiu Beznea > --- > > Changes in v5: > - used suspend capability of the controller to pause/resume > the transfers > > drivers/dma/sh/rz-dmac.c | 35 +++++++++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c > index c3035b94ef2c..e349ade1845f 100644 > --- a/drivers/dma/sh/rz-dmac.c > +++ b/drivers/dma/sh/rz-dmac.c > @@ -135,6 +135,7 @@ struct rz_dmac { > #define CHANNEL_8_15_COMMON_BASE 0x0700 > > #define CHSTAT_ER BIT(4) > +#define CHSTAT_SUS BIT(3) > #define CHSTAT_EN BIT(0) > > #define CHCTRL_CLRINTMSK BIT(17) > @@ -827,6 +828,38 @@ static enum dma_status rz_dmac_tx_status(struct dma_chan *chan, > return status; > } > > +static int rz_dmac_device_pause(struct dma_chan *chan) > +{ > + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); > + u32 val; > + > + scoped_guard(spinlock_irqsave, &channel->vc.lock) { > + val = rz_dmac_ch_readl(channel, CHCTRL, 1); > + val |= CHCTRL_CLRSUS; This is wrong, I overlooked it. It should have set the CHCTRL_SETSUS bit. > + rz_dmac_ch_writel(channel, val, CHCTRL, 1); > + } > + > + return read_poll_timeout_atomic(rz_dmac_ch_readl, val, > + (val & CHSTAT_SUS), 1, 1024, false, > + channel, CHSTAT, 1); > +} > + > +static int rz_dmac_device_resume(struct dma_chan *chan) > +{ > + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); > + u32 val; > + > + scoped_guard(spinlock_irqsave, &channel->vc.lock) { > + val = rz_dmac_ch_readl(channel, CHCTRL, 1); > + val &= ~CHCTRL_CLRSUS; Same here. It should have set the CHCTRL_CLRSUS bit. I'll update it in the next version. Thank you, Claudiu