From: Andrew Jeffery <andrew@codeconstruct.com.au>
To: Kevin Tung <kevin.tung.openbmc@gmail.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Joel Stanley <joel@jms.id.au>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,
Amithash Prasasd <amithash@meta.com>,
Kevin Tung <Kevin.Tung@quantatw.com>,
Ken Chen <Ken.Chen@quantatw.com>,
Leo Yang <Leo-Yang@quantatw.com>,
Jackson Liu <Jackson.Liu@quantatw.com>
Subject: Re: [PATCH] ARM: dts: aspeed: yosemite5: add x4 E1.S expansion board I2C mux
Date: Thu, 08 Jan 2026 15:16:19 +1030 [thread overview]
Message-ID: <a0d802a1e450860a9859ce3d456fcce81dde8ba3.camel@codeconstruct.com.au> (raw)
In-Reply-To: <20251222-yv5_add_dvt_e1s_ioexp-v1-1-25ad202d2681@gmail.com>
On Mon, 2025-12-22 at 19:25 +0800, Kevin Tung wrote:
> The new hardware design adds two additional E1.S devices behind an
> I2C mux at address 0x73 on bus 10. Add support for this mux in the
> DTS device tree.
Out of curiosity, you're monitoring them with the NVMe-MI basic
management command and not NVMe-MI over MCTP, or is there something
else going on which motivates describing empty mux legs?
Andrew
next prev parent reply other threads:[~2026-01-08 4:46 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-22 11:25 Kevin Tung
2026-01-08 4:46 ` Andrew Jeffery [this message]
2026-01-30 8:40 ` Kevin Tung
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