From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 598301E32D6 for ; Sat, 25 Jul 2026 07:38:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.49 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784965136; cv=none; b=h+ztYPIa6tABinPEeM2N8tOXgckpLflf/sJT24OKOfdjXtgP/DVdLCWHmm2F/Tc6VPWQ7/fPjMuIzgnM7SzqGS/AwLqlUhB0qV7Pj6ohkp1w9Po2QEPuoWxjNdabxufRr2uog8YA58EboegNdvgmEaAYpPSA3WecIIUuvjaeFok= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784965136; c=relaxed/simple; bh=VWMIk17SrSyGo5oTHUwCe4GU7j1K13mrWReRp5pKOUQ=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=dbpsKWg9jkbziTGXsWcKYispYdDpL55AQg1z45clDQVtvyPuw4ozL/U9U/J3CWfgon6X57guWVGS1//aP51SbO3PWLyNSa4xAwgZEwk+VQ6/DkP01grxafL3X/OP2dlP5vVnDGx5WSxXGHUHb/IW0UCI4dfCap6t96cbwls7xL4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=zIlpzSb3; arc=none smtp.client-ip=209.85.167.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zIlpzSb3" Received: by mail-lf1-f49.google.com with SMTP id 2adb3069b0e04-5aeb7ccb9f0so117230e87.0 for ; Sat, 25 Jul 2026 00:38:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1784965132; x=1785569932; darn=vger.kernel.org; h=content-transfer-encoding:content-type:in-reply-to:from:references :cc:to:subject:user-agent:mime-version:date:message-id:from:to:cc :subject:date:message-id:reply-to:content-type; bh=ATBMhXRdEW5TVTDYWajPFd+d4nyZcOHYkx9p8czNgDQ=; b=zIlpzSb3Wq75cYELT0cBFgIa/r3/2mY5/kaJM8klDxLmndcdvfhqtqlmhLLdMXBwX9 TeTIhy/w6dXPPA10828CtWi4WkdQ3o4T5HEWJokfPsc2Lh9FIa/bmtOTlxHEQKEY6oIW gwJZxEhyLtKwoAemHTO5tIk9gMNc/trR+5n85pkRJXCKifJ04VaQ/1BpSssgdL9oYSq+ AkMuHDstiLoRUY7GW/N+YduR1ynKRNxItNOo2HE79MC2xGas5sh6xgfn0A57l2fJtc+g oMVjg8VihFRDubKRpJc9gANnBa4nSVwFmSz0tU13dM+yf61FS/xc2dXHtvMLFmYTpa7I 6I0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784965132; x=1785569932; h=content-transfer-encoding:content-type:in-reply-to:from:references :cc:to:subject:user-agent:mime-version:date:message-id:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=ATBMhXRdEW5TVTDYWajPFd+d4nyZcOHYkx9p8czNgDQ=; b=C9QPq7KrVDiEP7sph6+VfJP7mJ/jmmipJczHUdMc1W4uLaufKr+SdOUCH+HgBjXJTy WkG/dcS2K8J5WA/6dfscLQkqwd4AJrEnhu5lBdny2ObrusCIXTqnSg0otJKJoN1s4fcl RmVlkVevg6ZL5BZWa6LccEnZdweoLrZCcnmCqkB9eKpJdbHiMVAc0C+rzdlZLepMO+i2 xPq3/Fy2FOk5L2WxBEfynKFlStQTSzYMnTwfiS1gAyVyweHvWKC4EvH2a5Hwwwkl6CnO JkWWfTCgr4vfskUe6lwVfPNzrBH7g/dZi2Il5ouL49+5xym5nw4wSmTaFl2L/OTnfp3N 8hMA== X-Forwarded-Encrypted: i=1; AHgh+Rqar3b1oOT2McqqwS0SuxkJ5NfmLhEoeSY+XqpA9QQwlDG/nmhzQDXsMQ4FQ5kT7wztZfScgFYmrgrn3WY=@vger.kernel.org X-Gm-Message-State: AOJu0YwlerOBa57Mga2izzeC0Ve52PLm1O47UxI+LcnTKt/xXDgCIDb0 npXLdvwKYag+c4KPj3SJUF3XX9c1pBZ1Nyvr6juRZL3aRb/ArKTAw1Gj9uymy/4Te4M= X-Gm-Gg: AR+sD13xLobwTCTDfAdFM9Ml/GStNW8jwPU4sfU4Pq/Khi3Tnu05Osenop7obAWDjtz C076z7dxRwUk9mKo95CUanoWePyfTsBv/PlF3AdmlWQqreFegkFXqiKYzLImIZzqTPWtr27pesp PVgYWNrv7ZrUqAuYhQNOF9c1OWguaGMo3XL/QAuTFcGqGfXwdlojKlhpUsnpZYXj9o49Ozn8gej 8Sd4G+iXFjTJt6+TcBLUEjs2tGLPUarF3sLruuFgACrvNJDomuQ8upg6m/EQi5+XUbQNDEt3AMR BaT8oEcV8BZalb4jCkL+LKolVvSQU4fEBPQiTMzZLYEZfR8YLLkVt/lNMTFhx349GJvpzUqb+6P IvOVF65wmoNpFABYFk/a0hd+XLdnMIfL5dys5VMzdT11wNlIsJ38ZWes2nkiu/4Mxb0Wp91GllH vst7oBycLf3EVBHxnLDn9CaD6YWGfKIa6mYkwxXXwpJaRb/n7kGrfwuZ/B X-Received: by 2002:a05:6512:a8a:b0:5ae:c8d9:f977 with SMTP id 2adb3069b0e04-5b2c1b3f4b2mr149566e87.8.1784965132239; Sat, 25 Jul 2026 00:38:52 -0700 (PDT) Received: from [192.168.1.100] (91-159-24-186.elisa-laajakaista.fi. [91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b2be0777e2sm330157e87.4.2026.07.25.00.38.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 25 Jul 2026 00:38:51 -0700 (PDT) Message-ID: Date: Sat, 25 Jul 2026 10:38:49 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 14/17] media: i2c: os05b10: add 2-lane support To: Tarang Raval , sakari.ailus@linux.intel.com, mehdi.djait@linux.intel.com Cc: Himanshu Bhavani , Elgin Perumbilly , Mauro Carvalho Chehab , Hans Verkuil , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260718200912.16001-1-tarang.raval@siliconsignals.io> <20260718200912.16001-15-tarang.raval@siliconsignals.io> From: Vladimir Zapolskiy In-Reply-To: <20260718200912.16001-15-tarang.raval@siliconsignals.io> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/18/26 23:09, Tarang Raval wrote: > Add support for 2-lane. > > Update link-frequency handling to select 750 MHz for 2-lane and 600 MHz for > 4-lane, and adjust pixel rate computation accordingly. Extend endpoint > parsing to accept 2 or 4 data lanes. > > Signed-off-by: Tarang Raval > --- > drivers/media/i2c/os05b10.c | 94 ++++++++++++++++++++++++++++--------- > 1 file changed, 71 insertions(+), 23 deletions(-) > > diff --git a/drivers/media/i2c/os05b10.c b/drivers/media/i2c/os05b10.c > index 876186b22f5f..6d91a9660660 100644 > --- a/drivers/media/i2c/os05b10.c > +++ b/drivers/media/i2c/os05b10.c > @@ -113,7 +113,8 @@ > #define OS05B10_TRANSPARENT_EFFECT 0xa0 > #define OS05B10_ROLLING_BAR_EFFECT 0xc0 > > -#define OS05B10_LINK_FREQ_600MHZ (600 * HZ_PER_MHZ) > +#define OS05B10_LINK_FREQ_4LANE (600 * HZ_PER_MHZ) > +#define OS05B10_LINK_FREQ_2LANE (750 * HZ_PER_MHZ) I believe the macro name shall be kept as is, frequency is not specific to the number of lanes, it's driver implementation/limitation specifics. > > static const struct v4l2_rect os05b10_native_area = { > .top = 0, > @@ -136,13 +137,7 @@ static const char * const os05b10_supply_name[] = { > }; > > static const struct cci_reg_sequence os05b10_common_regs[] = { > - { OS05B10_REG_PLL_CTRL_01, 0x44 }, > - { OS05B10_REG_PLL_CTRL_03, 0x02 }, > - { OS05B10_REG_PLL_CTRL_05, 0x32 }, > - { OS05B10_REG_PLL_CTRL_06, 0x00 }, > - { OS05B10_REG_PLL_CTRL_25, 0x3b }, > { CCI_REG8(0x3002), 0x21 }, > - { OS05B10_REG_MIPI_SC_CTRL, 0x72 }, > { CCI_REG8(0x301e), 0xb4 }, > { CCI_REG8(0x301f), 0xd0 }, > { CCI_REG8(0x3021), 0x03 }, > @@ -532,6 +527,24 @@ static const struct cci_reg_sequence mode_1280_720_regs[] = { > { CCI_REG8(0x4837), 0x0d }, > }; > > +static const struct cci_reg_sequence os05b10_2lane_regs[] = { > + { OS05B10_REG_PLL_CTRL_01, 0x44 }, > + { OS05B10_REG_PLL_CTRL_03, 0x02 }, > + { OS05B10_REG_PLL_CTRL_05, 0x64 }, > + { OS05B10_REG_PLL_CTRL_06, 0x00 }, > + { OS05B10_REG_PLL_CTRL_25, 0x3b }, > + { OS05B10_REG_MIPI_SC_CTRL, OS05B10_2_LANE_MODE }, > +}; > + > +static const struct cci_reg_sequence os05b10_4lane_regs[] = { > + { OS05B10_REG_PLL_CTRL_01, 0x44 }, > + { OS05B10_REG_PLL_CTRL_03, 0x02 }, > + { OS05B10_REG_PLL_CTRL_05, 0x32 }, > + { OS05B10_REG_PLL_CTRL_06, 0x00 }, > + { OS05B10_REG_PLL_CTRL_25, 0x3b }, > + { OS05B10_REG_MIPI_SC_CTRL, OS05B10_4_LANE_MODE }, > +}; > + > struct os05b10 { > struct device *dev; > struct regmap *cci; > @@ -650,8 +663,12 @@ static const struct os05b10_mode supported_modes_10bit[] = { > }, > }; > > -static const s64 link_frequencies[] = { > - OS05B10_LINK_FREQ_600MHZ, > +static const s64 link_frequencies_4lane[] = { > + OS05B10_LINK_FREQ_4LANE, > +}; > + > +static const s64 link_frequencies_2lane[] = { > + OS05B10_LINK_FREQ_2LANE, > }; Please just use macro with frequency in its name, or plainly use the intended frequencies here. > > static const u32 os05b10_mbus_codes[] = { > @@ -838,7 +855,9 @@ static int os05b10_enum_mbus_code(struct v4l2_subdev *sd, > static u64 os05b10_pixel_rate(struct os05b10 *os05b10, > const struct os05b10_mode *mode) > { > - u64 link_freq = link_frequencies[os05b10->link_freq_index]; > + u64 link_freq = (os05b10->data_lanes == 2) ? > + link_frequencies_2lane[os05b10->link_freq_index] : > + link_frequencies_4lane[os05b10->link_freq_index]; > u64 pixel_rate = div_u64(link_freq * 2 * os05b10->data_lanes, mode->bpp); > > dev_dbg(os05b10->dev, > @@ -983,6 +1002,17 @@ static int os05b10_enable_streams(struct v4l2_subdev *sd, > ret = pm_runtime_resume_and_get(os05b10->dev); > if (ret < 0) > return ret; > + /* Set pll & mipi lane configuration */ > + if (os05b10->data_lanes == 2) > + cci_multi_reg_write(os05b10->cci, os05b10_2lane_regs, > + ARRAY_SIZE(os05b10_2lane_regs), &ret); > + else > + cci_multi_reg_write(os05b10->cci, os05b10_4lane_regs, > + ARRAY_SIZE(os05b10_4lane_regs), &ret); > + if (ret) { > + dev_err(os05b10->dev, "failed to write pll & mipi lane registers\n"); > + goto err_rpm_put; > + } > > /* Write common registers */ > ret = cci_multi_reg_write(os05b10->cci, os05b10_common_regs, > @@ -1195,22 +1225,39 @@ static int os05b10_parse_endpoint(struct os05b10 *os05b10) > if (ret) > return ret; > > - if (bus_cfg.bus.mipi_csi2.num_data_lanes != 4) { > + if (bus_cfg.bus.mipi_csi2.num_data_lanes != 4 && > + bus_cfg.bus.mipi_csi2.num_data_lanes != 2) { > ret = dev_err_probe(os05b10->dev, -EINVAL, > - "only 4 data lanes are supported\n"); > + "4 and 2 data lanes are supported\n"); > goto error_out; > } > > os05b10->data_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes; > > - ret = v4l2_link_freq_to_bitmap(os05b10->dev, bus_cfg.link_frequencies, > - bus_cfg.nr_of_link_frequencies, > - link_frequencies, > - ARRAY_SIZE(link_frequencies), > - &link_freq_bitmap); > - if (ret) { > - dev_err(os05b10->dev, "only 600MHz frequency is available\n"); > - goto error_out; > + if (os05b10->data_lanes == 2) { > + ret = v4l2_link_freq_to_bitmap(os05b10->dev, > + bus_cfg.link_frequencies, > + bus_cfg.nr_of_link_frequencies, > + link_frequencies_2lane, > + ARRAY_SIZE(link_frequencies_2lane), > + &link_freq_bitmap); > + if (ret) { > + dev_err(os05b10->dev, > + "For 2 lane 750MHz frequency is available\n"); > + goto error_out; > + } > + } else { > + ret = v4l2_link_freq_to_bitmap(os05b10->dev, > + bus_cfg.link_frequencies, > + bus_cfg.nr_of_link_frequencies, > + link_frequencies_4lane, > + ARRAY_SIZE(link_frequencies_4lane), > + &link_freq_bitmap); > + if (ret) { > + dev_err(os05b10->dev, > + "For 4 lane 600MHz frequency is available\n"); > + goto error_out; > + } > } > > os05b10->link_freq_index = __ffs(link_freq_bitmap); > @@ -1240,10 +1287,11 @@ static int os05b10_init_controls(struct os05b10 *os05b10) > > os05b10->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &os05b10_ctrl_ops, > V4L2_CID_LINK_FREQ, > - ARRAY_SIZE(link_frequencies) - 1, > + ARRAY_SIZE(link_frequencies_4lane) - 1, > os05b10->link_freq_index, > - link_frequencies); > - > + (os05b10->data_lanes == 2) ? > + link_frequencies_2lane : > + link_frequencies_4lane); > if (os05b10->link_freq) > os05b10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; > -- Best wishes, Vladimir