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a="117413237" X-IronPort-AV: E=Sophos;i="6.27,208,1787004000"; d="scan'208";a="117413237" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO MUCSE812.infineon.com) ([172.23.29.38]) by smtp9.infineon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2026 01:15:03 +0100 Received: from MUCSE815.infineon.com (172.23.29.41) by MUCSE812.infineon.com (172.23.29.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.56; Thu, 12 Nov 2026 01:15:02 +0100 Received: from MUCSE815.infineon.com ([fe80::b54c:c0bd:546c:c9be]) by MUCSE815.infineon.com ([fe80::b54c:c0bd:546c:c9be%12]) with mapi id 15.02.2562.056; Thu, 12 Nov 2026 01:15:02 +0100 From: To: , , , , , CC: , Subject: RE: [PATCH v1 1/3] mtd: spi-nor: Support mixed 1S-xD-xD DTR protocols in spi_nor_spimem_setup_op() Thread-Topic: [PATCH v1 1/3] mtd: spi-nor: Support mixed 1S-xD-xD DTR protocols in spi_nor_spimem_setup_op() Thread-Index: AQHdccU7vDdb+C7/3E+0a9kRwM+hPrcpkglA Date: Thu, 12 Nov 2026 00:15:02 +0000 Message-ID: References: <20261111101240.7378-1-changhuang.liang@starfivetech.com> <20261111101240.7378-2-changhuang.liang@starfivetech.com> In-Reply-To: <20261111101240.7378-2-changhuang.liang@starfivetech.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 > Currently spi_nor_spimem_setup_op() sets all four phases (cmd, addr, > dummy, data) to DTR whenever spi_nor_protocol_is_dtr(proto) is true. > This is too coarse: the 1S-xD-xD DTR protocols (1_1_1_DTR, 1_2_2_DTR, > 1_4_4_DTR, 1_8_8_DTR) send the command phase in STR on a single line, > and only the address, dummy and data phases in DTR. SPIMEM supports > such mixed DTR modes. >=20 > Split the handling: >=20 > - For SNOR_PROTO_8_8_8_DTR, keep the existing behavior: set all > phases to DTR and use a 2-byte opcode (opcode + extension). >=20 > - For the other DTR protocols, set the command phase to STR and only > the address, dummy and data phases to DTR. Double op->dummy.nbytes > since DTR transfers 2 bytes per clock cycle, matching how the dummy > cycle count is specified for these protocols. >=20 > - Move the SWAP16 handling into the 8D-8D-8D branch as well, since > it only applies there. >=20 > No in-tree flash currently declares SNOR_HWCAPS_READ_1_x_x_DTR, so > this is not a bug fix but preparation for enabling these protocols. > A follow-up patch will enable 1S-4D-4D for the MX66L1G45G. The > 8D-8D-8D path is unchanged. >=20 > Signed-off-by: Changhuang Liang > --- Reviewed-by: Takahiro Kuwano