From: Jie Gan <quic_jiegan@quicinc.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>
Cc: "Jinlong Mao (QUIC)" <quic_jinlmao@quicinc.com>,
"coresight@lists.linaro.org" <coresight@lists.linaro.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"Tingwei Zhang (QUIC)" <quic_tingweiz@quicinc.com>,
"Yuanfang Zhang (QUIC)" <quic_yuanfang@quicinc.com>,
"Tao Zhang (QUIC)" <quic_taozha@quicinc.com>,
"Sam Chai (QUIC)" <quic_songchai@quicinc.com>,
"linux-arm-msm@vger.kernel.org" <linux-arm-msm@vger.kernel.org>,
"linux-stm32@st-md-mailman.stormreply.com"
<linux-stm32@st-md-mailman.stormreply.com>
Subject: Re: [PATCH v6 0/5] Coresight: Add Coresight TMC Control Unit driver
Date: Tue, 29 Oct 2024 10:45:23 +0800 [thread overview]
Message-ID: <a1400acb-e9e9-4233-8c0c-573be3e3370d@quicinc.com> (raw)
In-Reply-To: <20241009112503.1851585-1-quic_jiegan@quicinc.com>
On 10/9/2024 7:24 PM, Jie Gan wrote:
> The Coresight TMC Control Unit(CTCU) device hosts miscellaneous configuration
> registers to control various features related to TMC ETR device.
>
> The CTCU device works as a helper device physically connected to the TMC ETR device.
> ---------------------------------------------------------
> |ETR0| |ETR1|
> . \ / .
> . \ / .
> . \ / .
> . \ / .
> ---------------------------------------------------
> ETR0ATID0-ETR0ATID3 CTCU ETR1ATID0-ETR1ATID3
> ---------------------------------------------------
> Each ETR has four ATID registers with 128 bits long in total.
> e.g. ETR0ATID0-ETR0ATID3 registers are used by ETR0 device.
>
> Based on the trace id which is programed in CTCU ATID register of
> specific ETR, trace data with that trace id can get into ETR's buffer
> while other trace data gets ignored. The number of CTCU ATID registers
> depends on the number of defined TMC ETR devices. For example, two TMC
> ETR devices need eight ATID registers. ETR0 with ETR0ATID0-ETR0ATID3
> and ETR1 with ETR1ATID0-ETRATID3.
>
> The significant challenge in enabling the data filter function is how
> to collect the trace ID of the source device. The introduction of
> trace_id callback function addresses this challenge. The callback function
> collects trace ID of the device and return it back. The trace ID will be
> stored in the structure called cs_sink_data and transmitted to helper
> and sink devices.
>
> The cs_sink_data structure is created to address how to transmit
> parameters needs by coresight_enable_path/coresight_disbale_path
> functions.
>
> Here is an example of the struct cs_sink_data:
> struct cs_sink_data {
> struct perf_output_handle *handle; //used by perf mode
> struct coresight_device *sink; //used to retrieve atid_offset
> u32 traceid; //traceid needed by CTCU
> };
>
> The atid_offset mentioned before is the offset to ATID register in CTCU
> device.
>
> Enabling the source device will configure one bit in the ATID register based
> on its trace ID.
> Disabling the source devices will reset the bit in the AITD register
> based on its trace ID.
>
[...]
Kindly remainder, Please help to review the patch series.
Thanks,
Jie
prev parent reply other threads:[~2024-10-29 2:45 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-09 11:24 Jie Gan
2024-10-09 11:24 ` [PATCH v6 1/5] Coresight: Add support for new APB clock name Jie Gan
2024-10-09 11:25 ` [PATCH v6 2/5] Coresight: Add trace_id function to retrieving the trace ID Jie Gan
2024-10-09 11:25 ` [PATCH v6 3/5] dt-bindings: arm: Add Coresight TMC Control Unit hardware Jie Gan
2024-10-09 11:25 ` [PATCH v6 4/5] Coresight: Add Coresight TMC Control Unit driver Jie Gan
2024-10-09 11:25 ` [PATCH v6 5/5] arm64: dts: qcom: Add CTCU and ETR nodes for SA8775p Jie Gan
2024-10-29 2:45 ` Jie Gan [this message]
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