From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C5E6384CE5 for ; Tue, 11 Aug 2026 15:05:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786460710; cv=none; b=XxF8ShXp1UNfvW9/KKToPGLUUptnTKBDXbIwvCJnxJT9eLmxy8CfM5y2Lggqg2Cm6+PMNi9ZHR53l4oBjKhkd1U+lHm6L5lpcj0cVGVz/bSJZB6vTkE1xortH48ETC3iL/N5+axg8ihQ6AuBLGB85ddc3ghIVf4dL9W62Ie7Q4M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786460710; c=relaxed/simple; bh=sDwWMi0ek/uwM/uApZ8azvqnot6VNZHUOSVgn+EXtyA=; h=MIME-Version:Date:From:To:Cc:Message-Id:In-Reply-To:References: Subject:Content-Type; b=NrG6m2/kUohUPwprOPIuMB7i8hgi+0eQecGTFcTCiSkxv8FQW+I3Lh7xIzl1GLLZ1FrjC1whKyWnN9cnuXhqVVjrZc7mbtNe0xMEiKzt8Lp+AAE5Y9SipEY05zYq0egwPVoujRZqrzZWB2KGjL5u3gl01ykrYBT3hB0WVCSKHoY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FzvBZJHL; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FzvBZJHL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0447C1F000E9; Tue, 11 Aug 2026 15:05:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786460709; bh=cuJIf2aoBaJ6kPCjr/Pql12UXi9Q+aLNH7PnF7eMFVw=; h=Date:From:To:Cc:In-Reply-To:References:Subject; b=FzvBZJHLjxF6MSUz0zXv+SF4BGkk+l60a9iK0ynAK3FQrCkpIktRS42+EF3qcnBzR 1fS1XhWAaumtbKDqxthjKv8ctxBOffEva3kxusutK1hDxhxh0uHo7Be6n1k6GNNR1E 3Wr3ZjnFAACU3Na0bFP243MP39o+RObKp7CkzCRiBFXAUqXOpELq26QI1gjQgZ+7gf mO8ka/GQZkW8Bu/wqpZ4kzw4xGn7qkes5yrZEvDFEC5WGtxuxr1LZzE21zQmfFpFBL LJug4isqEjg/8/MGj+gv7nDyupw1rLR3Y4cOgK/QkdbWt9MjonIYKkWTuVkA90hSu2 5Z7RwD8QSMAHg== Received: from ams-compute-02.internal (ams-compute-02.internal [10.64.2.62]) by mailfauth.ams.internal (Postfix) with ESMTP id A6532198003A; Tue, 11 Aug 2026 11:05:06 -0400 (EDT) Received: from ams-imap-11 ([10.64.2.31]) by ams-compute-02.internal (MEProxy); Tue, 11 Aug 2026 11:05:06 -0400 X-ME-Sender: X-ME-Proxy-Cause: dmFkZTGRQrvTqj4nIxnBKZouz0SX5s2ZjoZ7nSFEG3l9OO77VZpVPLA/jn1cTOIiAEXUKX K2ftnlB35lAHgdnpgJNXqXn1FBo8DAIzVHrgBz0jc6w8gofPFoJvMNVdrnkYjIaBsmrwMa MKvUrjMOztwtjXlcCnDEOVJPTepLaxy1bx1COwCwRhsp4/iVyv0JOoG6HKSVdEeK6ONY4q ogX84oZC4/KXXs16WHMMRFgrxKvq7t6Tn9OtaptXwAMsSkZ/a3/W29IfqUD6oruHG1AM+g DOcH7VcizzefX3EOZKEP+KgdwbgFIPrZef1+s0JJpfxPHUjEVK7veUdNdipzaijBK11HAe PYz5lzOlSFuDNBIlNgtEBVIblIqqiCkgsywZ/+pRCyElxe+sTqMmQLcsMaQvFYfMzt5NRG D2EuHNbXPQhdoD2RuQPCuCwObePYpN2m8/bT3QGcEtic6tub5WAGyUXMFqvtLbbHqjUgY4 KkH/VhOHWtQFuE1ry2zwPiSVKZW6rIbHF73MoNlmSNHe/TjjFD54olBSPnvTNFhjEp5OlI ovWuSVJnhjADcrwhk0W0CErXLZlkm6Nbzdi1eAfjLllC0i5kYsg4J0pv93lQh4wP7tTNdA MSogLa48oFy2UE3bFZB1wH1ofmWMgwABEPfHEgNp5W/XANux/TVqhg0h8LIA X-ME-Proxy: Feedback-ID: ice86485a:Fastmail Received: by mailuser.ams.internal (Postfix, from userid 501) id 0B92CF8006E; Tue, 11 Aug 2026 11:05:04 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 11 Aug 2026 17:04:43 +0200 From: "Ard Biesheuvel" To: "Will Deacon" , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, "Arnd Bergmann" , "Eric Biggers" , "Daniel Borkmann" , "Catalin Marinas" , "Alexei Starovoitov" , "Oliver Upton" , "Herbert Xu" , "Marc Zyngier" Message-Id: In-Reply-To: <20260811140132.22778-7-will@kernel.org> References: <20260811140132.22778-1-will@kernel.org> <20260811140132.22778-7-will@kernel.org> Subject: Re: [PATCH 06/12] arm64: assembler: Remove endianness helper macros Content-Type: text/plain Content-Transfer-Encoding: 7bit On Tue, 11 Aug 2026, at 16:01, Will Deacon wrote: > The CPU_LE()/CPU_BE() helper macros are only used by head.S. Since > big-endian support depends on BROKEN, remove the last users along with > the macro definitions. The unused regs_to_64() assembly macro, which > somewhat bizarrely behaves differently depend on the endianness, is also > removed. > > Signed-off-by: Will Deacon > --- > arch/arm64/include/asm/assembler.h | 31 ------------------------------ > arch/arm64/kernel/head.S | 3 +-- > 2 files changed, 1 insertion(+), 33 deletions(-) > > diff --git a/arch/arm64/include/asm/assembler.h > b/arch/arm64/include/asm/assembler.h > index effae53e9739..45279e577ff5 100644 > --- a/arch/arm64/include/asm/assembler.h > +++ b/arch/arm64/include/asm/assembler.h > @@ -133,37 +133,6 @@ lr .req x30 // link register > b \label > .endm > > -/* > - * Select code when configured for BE. > - */ > -#ifdef CONFIG_CPU_BIG_ENDIAN > -#define CPU_BE(code...) code > -#else > -#define CPU_BE(code...) > -#endif > - > -/* > - * Select code when configured for LE. > - */ > -#ifdef CONFIG_CPU_BIG_ENDIAN > -#define CPU_LE(code...) > -#else > -#define CPU_LE(code...) code > -#endif > - > -/* > - * Define a macro that constructs a 64-bit value by concatenating two > - * 32-bit registers. Note that on big endian systems the order of the > - * registers is swapped. > - */ > -#ifndef CONFIG_CPU_BIG_ENDIAN > - .macro regs_to_64, rd, lbits, hbits > -#else > - .macro regs_to_64, rd, hbits, lbits > -#endif > - orr \rd, \lbits, \hbits, lsl #32 > - .endm > - > /* > * Pseudo-ops for PC-relative adr/ldr/str , where > * is within the range +/- 4 GB of the PC. > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S > index 87a822e5c4ca..8951ce693552 100644 > --- a/arch/arm64/kernel/head.S > +++ b/arch/arm64/kernel/head.S > @@ -138,8 +138,7 @@ SYM_CODE_START_LOCAL(record_mmu_state) > b.ne 0f > mrs x19, sctlr_el2 > 0: > -CPU_LE( tbnz x19, #SCTLR_ELx_EE_SHIFT, 1f ) > -CPU_BE( tbz x19, #SCTLR_ELx_EE_SHIFT, 1f ) > + tbnz x19, #SCTLR_ELx_EE_SHIFT, 1f > tst x19, #SCTLR_ELx_C // Z := (C == 0) > and x19, x19, #SCTLR_ELx_M // isolate M bit > csel x19, xzr, x19, eq // clear x19 if Z There is some more code that can be removed here - see 2ced0f30a426c7301350681f838344d5aea711e3