From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C8C8C433E3 for ; Fri, 7 Aug 2020 16:03:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1CAAC2224D for ; Fri, 7 Aug 2020 16:03:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="E3DUFXe2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726352AbgHGQDJ (ORCPT ); Fri, 7 Aug 2020 12:03:09 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:16539 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725815AbgHGQDI (ORCPT ); Fri, 7 Aug 2020 12:03:08 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 07 Aug 2020 09:02:54 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 07 Aug 2020 09:03:08 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 07 Aug 2020 09:03:08 -0700 Received: from [10.26.73.183] (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 7 Aug 2020 16:03:02 +0000 Subject: Re: [Patch v2 2/4] dmaengine: tegra: Add Tegra GPC DMA driver To: Rajesh Gumasta , , , , , , , , CC: , Pavan Kunapuli References: <1596699006-9934-1-git-send-email-rgumasta@nvidia.com> <1596699006-9934-3-git-send-email-rgumasta@nvidia.com> From: Jon Hunter Message-ID: Date: Fri, 7 Aug 2020 17:03:00 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <1596699006-9934-3-git-send-email-rgumasta@nvidia.com> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596816174; bh=IVGky6nLxDkiBaaxwKtT2L98g021B3TbNVb8iaX+a2o=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=E3DUFXe2pxHisbdIwV064pYOFGdAw6mnlEJkWxAQ85aIX47ja5/IP8Xhv0Ec994PI ZDoY2gg66kN/PS+7jgSsANnVuVS3K1XQJnY5RYEVgLNTbog2pb+wDSwF2d03u+u786 wmHBVbPzdpCYy9nxCaYtF21OF5YhGxPNBnmHri8cfltygKf1+MKC2XUcHJDzWwnRex MQC0reaONUHiXKyH6ZEszDimpVGE1f9C0EOkfdavFnKtkTWDzCheWoll0THA3qYj9m 3+WOeHN8naScraT8fe6rhIaLq26g5l1550Ot+NRupYeCC5pHwJAOSMkkK1Zwd4bXH+ V/CnwGhLW+2Sw== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/08/2020 08:30, Rajesh Gumasta wrote: > Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver > supports dma transfers between memory to memory, IO peripheral to memory > and memory to IO peripheral. > > Signed-off-by: Pavan Kunapuli > Signed-off-by: Rajesh Gumasta > --- > drivers/dma/Kconfig | 12 + > drivers/dma/Makefile | 1 + > drivers/dma/tegra-gpc-dma.c | 1472 +++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 1485 insertions(+) > create mode 100644 drivers/dma/tegra-gpc-dma.c ... > +static void tdc_start_head_req(struct tegra_dma_channel *tdc) > +{ > + struct tegra_dma_sg_req *sg_req; > + struct virt_dma_desc *vdesc; > + > + if (list_empty(&tdc->pending_sg_req)) > + return; > + > + if (tdc->is_pending) > + return; > + > + vdesc = vchan_next_desc(&tdc->vc); > + if (!vdesc) > + return; > + list_del(&vdesc->node); > + tdc->dma_desc = vd_to_tegra_dma_desc(vdesc); > + tdc->is_pending = true; > + tdc->dma_desc->tdc = tdc; > + sg_req = list_first_entry(&tdc->pending_sg_req, > + typeof(*sg_req), node); > + tegra_dma_start(tdc, sg_req); > + sg_req->configured = true; > + tdc->busy = true; > +} I really don't understand this. First we get a descriptor for the vchan_next_desc and then we get a sg_req from another list. I really don't see why we need to have two lists here. Seems overly complicated. Jon -- nvpublic