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From: "Suthikulpanit, Suravee" <suravee.suthikulpanit@amd.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
	joro@8bytes.org, robin.murphy@arm.com, vasant.hegde@amd.com,
	kevin.tian@intel.com, jon.grimm@amd.com, santosh.shukla@amd.com,
	pandoh@google.com, kumaranand@google.com
Subject: Re: [PATCH v8 06/10] iommu/amd: Modify set_dte_entry() to use 256-bit DTE helpers
Date: Fri, 1 Nov 2024 22:02:44 +0700	[thread overview]
Message-ID: <a1e63536-9450-4081-9a3a-dae387d939d6@amd.com> (raw)
In-Reply-To: <20241101121022.GT10193@nvidia.com>



On 11/1/2024 7:10 PM, Jason Gunthorpe wrote:
> On Thu, Oct 31, 2024 at 06:42:39PM +0000, Suravee Suthikulpanit wrote:
>> +struct dev_table_entry *amd_iommu_get_ivhd_dte_flags(u16 segid, u16 devid)
>> +{
>> +	struct ivhd_dte_flags *e;
>> +	unsigned int best_len = UINT_MAX;
>> +	struct dev_table_entry *dte = NULL;
>> +
>> +	for_each_ivhd_dte_flags(e) {
>> +		/*
>> +		 * Need to go through the whole list to find the smallest range,
>> +		 * which contains the devid.
>> +		 */
>> +		if ((e->segid == segid) &&
>> +		    (e->devid_first >= devid) &&
>> +		    (e->devid_last <= devid)) {
> 
> Again, I don't know much about this format, but are you sure about
> this logic? Consider:
> 
>   e->devid_first = 10
>   devid = 12
>   e->devid_last = 15
> 
>   (e->devid_first >= devid) == 10 >= 12 == FALSE
>   (e->devid_last <= devid) == 15 <= 12 == FALSE
> 
> FALSE && FALSE == FALSE
> 
> It seems to me it does not do what the comment says? Compare to the
> version I sent in my last email

Ah, sorry again for this stupid mistake. You are correct. Thank you very 
much for catching this. I am sending V9 with only the fix for this.

Thanks,
Suravee

  reply	other threads:[~2024-11-01 15:02 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-31 18:42 [PATCH v8 00/10] iommu/amd: Use 128-bit cmpxchg operation to update DTE Suravee Suthikulpanit
2024-10-31 18:42 ` [PATCH v8 01/10] iommu/amd: Misc ACPI IVRS debug info clean up Suravee Suthikulpanit
2024-10-31 18:42 ` [PATCH v8 02/10] iommu/amd: Disable AMD IOMMU if CMPXCHG16B feature is not supported Suravee Suthikulpanit
2024-10-31 18:42 ` [PATCH v8 03/10] asm/rwonce: Introduce [READ|WRITE]_ONCE() support for __int128 Suravee Suthikulpanit
2024-10-31 18:42 ` [PATCH v8 04/10] iommu/amd: Introduce struct ivhd_dte_flags to store persistent DTE flags Suravee Suthikulpanit
2024-10-31 18:42 ` [PATCH v8 05/10] iommu/amd: Introduce helper function to update 256-bit DTE Suravee Suthikulpanit
2024-10-31 18:42 ` [PATCH v8 06/10] iommu/amd: Modify set_dte_entry() to use 256-bit DTE helpers Suravee Suthikulpanit
2024-11-01 12:10   ` Jason Gunthorpe
2024-11-01 15:02     ` Suthikulpanit, Suravee [this message]
2024-10-31 18:42 ` [PATCH v8 07/10] iommu/amd: Introduce helper function get_dte256() Suravee Suthikulpanit
2024-10-31 18:42 ` [PATCH v8 08/10] iommu/amd: Modify clear_dte_entry() to avoid in-place update Suravee Suthikulpanit
2024-10-31 18:42 ` [PATCH v8 09/10] iommu/amd: Lock DTE before updating the entry with WRITE_ONCE() Suravee Suthikulpanit
2024-10-31 18:42 ` [PATCH v8 10/10] iommu/amd: Remove amd_iommu_apply_erratum_63() Suravee Suthikulpanit

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