From: Andrew Cooper <Andrew.Cooper3@citrix.com>
To: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: Borislav Petkov <bp@alien8.de>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
"x86@kernel.org" <x86@kernel.org>,
"H. Peter Anvin" <hpa@zytor.com>,
"Andi Kleen" <ak@linux.intel.com>,
Tony Luck <tony.luck@intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"antonio.gomez.iglesias@linux.intel.com"
<antonio.gomez.iglesias@linux.intel.com>,
"neelima.krishnan@intel.com" <neelima.krishnan@intel.com>,
"stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: Re: [PATCH] x86/tsx: Use MSR_TSX_CTRL to clear CPUID bits
Date: Wed, 16 Feb 2022 11:46:17 +0000 [thread overview]
Message-ID: <a1e836c5-e2d0-3916-ec11-9f8690463c58@citrix.com> (raw)
In-Reply-To: <20220216012841.vxlnugre2j4pczp7@guptapa-mobl1.amr.corp.intel.com>
On 16/02/2022 01:28, Pawan Gupta wrote:
> On 16.02.2022 00:49, Andrew Cooper wrote:
>> On 16/02/2022 00:39, Pawan Gupta wrote:
>>> On 15.02.2022 20:33, Borislav Petkov wrote:
>>>> On Tue, Feb 15, 2022 at 10:19:31AM -0800, Pawan Gupta wrote:
>>>>> I admit it has gotten complicated with so many bits associated with
>>>>> TSX.
>>>>
>>>> Yah, and looka here:
>>>>
>>>> https://github.com/andyhhp/xen/commit/ad9f7c3b2e0df38ad6d54f4769d4dccf765fbcee
>>>>
>>>>
>>>>
>>>> It seems it isn't complicated enough. ;-\
>>>>
>>>> Andy just made me aware of this thing where you guys have added a new
>>>> MSR bit:
>>>>
>>>> MSR_MCU_OPT_CTRL[1] which is called something like
>>>> MCU_OPT_CTRL_RTM_ALLOW or so.
>>>
>>> RTM_ALLOW bit was added to MSR_MCU_OPT_CTRL, but its not set by
>>> default,
>>> and it is *not* recommended to be used in production deployments [1]:
>>>
>>> Although MSR 0x122 (TSX_CTRL) and MSR 0x123 (IA32_MCU_OPT_CTRL)
>>> can be
>>> used to reenable Intel TSX for development, doing so is not
>>> recommended
>>> for production deployments. In particular, applying MD_CLEAR flows
>>> for
>>> mitigation of the Intel TSX Asynchronous Abort (TAA) transient
>>> execution
>>> attack may not be effective on these processors when Intel TSX is
>>> enabled with updated microcode. The processors continue to be
>>> mitigated
>>> against TAA when Intel TSX is disabled.
>>
>> The purpose of setting RTM_ALLOW isn't to enable TSX per say.
>>
>> The purpose is to make MSR_TSX_CTRL.RTM_DISABLE behaves consistently on
>> all hardware, which reduces the complexity and invasiveness of dealing
>> with this special case, because the TAA workaround will still turn TSX
>> off by default.
>>
>> The configuration you don't want to be running with is RTM_ALLOW &&
>> !RTM_DISABLE, because that is "still vulnerable to TSX Async Abort".
>
> I am not sure how a system can end up with RTM_ALLOW && !RTM_DISABLE? I
> have no problem taking care of this case, I am just debating why we need
> it.
Well for one, when Linux is starting up as the kexec environment
following Xen.
You're not coding for "what logic should follow a clean microcode
load". You're coding for "how to take the arbitrary state that my
preceding environment left, and turn it into what I want".
Look no further than linuxboot for an environment where your bootloader
has already altered these settings.
~Andrew
next prev parent reply other threads:[~2022-02-16 11:47 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-09 21:04 Pawan Gupta
2022-02-14 17:38 ` Borislav Petkov
2022-02-14 22:41 ` Pawan Gupta
2022-02-14 23:28 ` Borislav Petkov
2022-02-15 0:20 ` Pawan Gupta
2022-02-15 10:24 ` Borislav Petkov
2022-02-15 12:11 ` Pawan Gupta
2022-02-15 16:31 ` Borislav Petkov
2022-02-15 18:19 ` Pawan Gupta
2022-02-15 19:33 ` Borislav Petkov
2022-02-16 0:39 ` Pawan Gupta
2022-02-16 0:49 ` Andrew Cooper
2022-02-16 1:28 ` Pawan Gupta
2022-02-16 6:08 ` Pawan Gupta
2022-02-16 10:30 ` Borislav Petkov
2022-02-16 19:03 ` Pawan Gupta
2022-02-16 11:46 ` Andrew Cooper [this message]
2022-02-16 18:59 ` Pawan Gupta
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