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Mon, 12 Oct 2026 15:41:03 -0500 Message-ID: Date: Mon, 12 Oct 2026 13:41:08 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH V4 04/19] accel/amdxdna: Support firmware 6.0 Content-Language: en-US To: David Zhang , , , , , , CC: , References: <20261009225343.3079074-1-yidong.zhang@amd.com> <20261009225343.3079074-5-yidong.zhang@amd.com> From: Lizhi Hou In-Reply-To: <20261009225343.3079074-5-yidong.zhang@amd.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E65:EE_|BY5PR12MB4130:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f2c2d60-8089-40e5-f2ce-08df28a125fb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|376014|36860700016|82310400026|56012099006|4143699003|11063799006|261009223027099003|22082099003|10067099003|18002099003|3023799007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SYfBbw8nH+pn3aZ/q6tFIUCAvwIcztZ9TUqu0JKU+iYfi9er8JCoj5Idz51XFcvDC/ZMQSUl1/hoi1SpDHhmr+ApLi5FgJStwiGMcKPeR7ZzkCV2pOuZYzQ7kt0lj4GUmza9e4qYkyun61eJV8DUq+lgIXXo+5SVkFLefzxwcSZALxKdAdKDCqdUA4tMvjWNfvHu7Dr6GV0OgFQGnv5z0P5YrrRh0PVrLhI/8BBsuSqZpvSbguTy1chBDQL2msj3lQTgCZYbzu2eZJBCSScmXUd3MKm1HAPRiEn2k3MJNw6zhXH9qYLoYYLgE++N+QEK0fQYs/NtPFBHInBBtNUZ1l7QW83/25vQzstAxUYsSP+omZFBJXgSC9FkYHAbXcLWRc9wItAUXJvLg/Ub7XHponXxyAx7HBTJnfQD2+tL1KPdbbpZBpe0vZAwqWhPjuZz X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Oct 2026 20:41:10.0650 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f2c2d60-8089-40e5-f2ce-08df28a125fb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E65.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4130 On 10/9/26 15:53, David Zhang wrote: > Support firmware interface version 6.0. Update host queue layout, > opcode definitions, and context creation/destruction request structures. > Parse priority band and PASID for hardware context creation. Protocol > compatibility for this queue layout is validated against the CERT > firmware protocol version. > > Signed-off-by: David Zhang Reviewed-by: Lizhi Hou > --- > drivers/accel/amdxdna/aie4_ctx.c | 23 ++++++++++++++++++++--- > drivers/accel/amdxdna/aie4_host_queue.h | 7 +++++-- > drivers/accel/amdxdna/aie4_message.c | 11 +++++++++++ > drivers/accel/amdxdna/aie4_msg_priv.h | 20 +++++++++++++++++--- > drivers/accel/amdxdna/aie4_pci.h | 1 + > drivers/accel/amdxdna/npu3_regs.c | 2 +- > 6 files changed, 55 insertions(+), 9 deletions(-) > > diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c > index 8157f2a6fd10..5eb918e1d58c 100644 > --- a/drivers/accel/amdxdna/aie4_ctx.c > +++ b/drivers/accel/amdxdna/aie4_ctx.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > #include > > #include "aie.h" > @@ -110,6 +111,22 @@ static int aie4_msg_destroy_context(struct amdxdna_dev_hdl *ndev, u32 hw_context > return aie_send_mgmt_msg_wait(&ndev->aie, &msg); > } > > +static u8 aie4_parse_priority_to_dev(u32 priority) > +{ > + switch (priority) { > + case AMDXDNA_QOS_LOW_PRIORITY: > + return AIE4_CONTEXT_PRIORITY_BAND_IDLE; > + case AMDXDNA_QOS_NORMAL_PRIORITY: > + return AIE4_CONTEXT_PRIORITY_BAND_NORMAL; > + case AMDXDNA_QOS_HIGH_PRIORITY: > + return AIE4_CONTEXT_PRIORITY_BAND_FOCUS; > + case AMDXDNA_QOS_REALTIME_PRIORITY: > + return AIE4_CONTEXT_PRIORITY_BAND_REAL_TIME; > + default: > + return AIE4_CONTEXT_PRIORITY_BAND_NORMAL; > + } > +} > + > static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx) > { > DECLARE_AIE_MSG(aie4_msg_create_hw_context, AIE4_MSG_OP_CREATE_HW_CONTEXT); > @@ -129,9 +146,9 @@ static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx) > > req.partition_id = ndev->partition_id; > req.request_num_tiles = hwctx->num_tiles; > - req.pasid = FIELD_PREP(AIE4_MSG_PASID, client->pasid) | > - FIELD_PREP(AIE4_MSG_PASID_VLD, 1); > - req.priority_band = hwctx->qos.priority; > + req.pasid = aie4_msg_pasid(client); > + req.pasid = req.pasid == IOMMU_PASID_INVALID ? 0 : req.pasid; > + req.priority_band = aie4_parse_priority_to_dev(hwctx->qos.priority); > > req.hsa_addr_high = upper_32_bits(amdxdna_gem_dev_addr(priv->umq_bo)); > req.hsa_addr_low = lower_32_bits(amdxdna_gem_dev_addr(priv->umq_bo)); > diff --git a/drivers/accel/amdxdna/aie4_host_queue.h b/drivers/accel/amdxdna/aie4_host_queue.h > index 1b33eda3f727..95ebbb714c6f 100644 > --- a/drivers/accel/amdxdna/aie4_host_queue.h > +++ b/drivers/accel/amdxdna/aie4_host_queue.h > @@ -10,6 +10,7 @@ > > #define CTX_MAX_CMDS 32 > > +/* Host queue header layout. */ > struct host_queue_header { > __u64 read_index; > struct { > @@ -17,8 +18,10 @@ struct host_queue_header { > __u16 minor; > } version; > __u32 capacity; /* Queue capacity, must be power of two. */ > - __u64 write_index; > + __u64 padding0[6]; > + __u64 write_index; /* different cacheline from read_index to avoid false sharing */ > + __u64 padding1[6]; > __u64 data_address; /* The xdna dev addr for payload. */ > -}; > +} __packed; > > #endif /* _AIE4_HOST_QUEUE_H_ */ > diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c > index 53f8e366b66c..f67aa8ba943c 100644 > --- a/drivers/accel/amdxdna/aie4_message.c > +++ b/drivers/accel/amdxdna/aie4_message.c > @@ -5,6 +5,8 @@ > > #include > #include > +#include > +#include > #include > > #include "aie.h" > @@ -14,6 +16,15 @@ > #include "amdxdna_mailbox_helper.h" > #include "amdxdna_pci_drv.h" > > +u32 aie4_msg_pasid(struct amdxdna_client *client) > +{ > + if (!amdxdna_pasid_on(client)) > + return IOMMU_PASID_INVALID; > + > + return FIELD_PREP(AIE4_MSG_PASID, client->pasid) | > + FIELD_PREP(AIE4_MSG_PASID_VLD, 1); > +} > + > int aie4_suspend_fw(struct amdxdna_dev_hdl *ndev) > { > DECLARE_AIE_MSG(aie4_msg_suspend, AIE4_MSG_OP_SUSPEND); > diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h > index 5b97c8057de0..b9f7c61f36e3 100644 > --- a/drivers/accel/amdxdna/aie4_msg_priv.h > +++ b/drivers/accel/amdxdna/aie4_msg_priv.h > @@ -12,7 +12,6 @@ > enum aie4_msg_opcode { > AIE4_MSG_OP_IDENTIFY = 0x10002, > AIE4_MSG_OP_SUSPEND = 0x10003, > - AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x1000D, > AIE4_MSG_OP_QUERY_CERT_FIRMWARE_VERSION = 0x1000F, > > AIE4_MSG_OP_CREATE_VFS = 0x20001, > @@ -23,6 +22,8 @@ enum aie4_msg_opcode { > AIE4_MSG_OP_CREATE_HW_CONTEXT = 0x30003, > AIE4_MSG_OP_DESTROY_HW_CONTEXT = 0x30004, > AIE4_MSG_OP_AIE_TILE_INFO = 0x30006, > + > + AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x40001, > }; > > enum aie4_msg_status { > @@ -32,6 +33,14 @@ enum aie4_msg_status { > MAX_AIE4_MSG_STATUS_CODE = 0x4, > }; > > +enum aie4_msg_context_priority_band { > + AIE4_CONTEXT_PRIORITY_BAND_IDLE = 0, > + AIE4_CONTEXT_PRIORITY_BAND_NORMAL, > + AIE4_CONTEXT_PRIORITY_BAND_FOCUS, > + AIE4_CONTEXT_PRIORITY_BAND_REAL_TIME, > + AIE4_CONTEXT_PRIORITY_BAND_COUNT > +}; > + > struct aie4_msg_identify_req { > __u32 rsvd; > } __packed; > @@ -94,7 +103,9 @@ struct aie4_msg_create_hw_context_req { > #define AIE4_MSG_PASID GENMASK(19, 0) > #define AIE4_MSG_PASID_VLD GENMASK(31, 31) > __u32 pasid; > - __u32 priority_band; > + __u8 priority_band; > + __u8 priority_level; > + __u16 restore_id; > } __packed; > > struct aie4_msg_create_hw_context_resp { > @@ -106,11 +117,14 @@ struct aie4_msg_create_hw_context_resp { > > struct aie4_msg_destroy_hw_context_req { > __u32 hw_context_id; > - __u32 resvd1; > +#define AIE4_MSG_GRACEFUL_FLAG GENMASK(0, 0) > + __u32 graceful_flag; > } __packed; > > struct aie4_msg_destroy_hw_context_resp { > enum aie4_msg_status status; > + __u16 restore_id; > + __u16 resvd; > } __packed; > > struct aie4_tile_info { > diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h > index 8c62ee6a9b23..bdbb2d7cf0e7 100644 > --- a/drivers/accel/amdxdna/aie4_pci.h > +++ b/drivers/accel/amdxdna/aie4_pci.h > @@ -75,6 +75,7 @@ int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev, > struct amdxdna_drm_query_firmware_version *fw_version); > int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev, > struct amdxdna_drm_query_firmware_version *cert_version); > +u32 aie4_msg_pasid(struct amdxdna_client *client); > > /* aie4_ctx.c */ > int aie4_hwctx_init(struct amdxdna_hwctx *hwctx); > diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c > index e82bc0a4f597..93f749acb5d5 100644 > --- a/drivers/accel/amdxdna/npu3_regs.c > +++ b/drivers/accel/amdxdna/npu3_regs.c > @@ -38,7 +38,7 @@ > #define MP1_C2PMSG_60_ALT_1 0x3B109F0 > > static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = { > - { .major = 5, .min_minor = 10 }, > + { .major = 6, .min_minor = 0 }, > { 0 } > }; >