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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-611c976f333sm803699a12.64.2025.07.10.05.29.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Jul 2025 05:29:47 -0700 (PDT) Message-ID: Date: Thu, 10 Jul 2025 14:29:44 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/4] phy: qcom: phy-qcom-snps-eusb2: Add extra register write for Milos To: Luca Weiss , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Vinod Koul , Kishon Vijay Abraham I , Abel Vesa Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Neil Armstrong References: <20250709-sm7635-eusb-phy-v2-0-4790eeee7ae0@fairphone.com> <20250709-sm7635-eusb-phy-v2-4-4790eeee7ae0@fairphone.com> <7d073433-f254-4d75-a68b-d184f900294a@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: GGavceq92ibG3_fWIaSJ62aq5uaYyDbB X-Authority-Analysis: v=2.4 cv=W7k4VQWk c=1 sm=1 tr=0 ts=686fb23d cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=KKAkSRfTAAAA:8 a=6H0WHjuAAAAA:8 a=RC4AtmPg6BGSdlR6CyEA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=cvBusfyB2V15izCimMoJ:22 a=Soq9LBFxuPC4vsCAQt-j:22 X-Proofpoint-ORIG-GUID: GGavceq92ibG3_fWIaSJ62aq5uaYyDbB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzEwMDEwNiBTYWx0ZWRfX6qN8sIATMhBR WFvee148IFGJAjrYvKUjzBqg4gbWvgIvexZLYlHP1euFbLOo4GMBwoCS93DHAOYgHrg50+iFjst Bmors2t+9c5v1QVtwMFyXE3+3h0vZ7sRahS5TAe9yvegBL65Y1cL7ev0WXTIX1V4qro85CozStb nhByFMONy7RLF83wC7wYoz6dULJlGt1MTh62F1Nu94sm2ncz4h5kqXBjILAcNGTdMX4Uvj+Qay6 dQ6w8bNgyDMqIoXESS7Fc9gMEhVeiwcyMzvUxMOkjWy9NXNYUcrq2fLVOCDojtK4fFubiLyq4aL BrQ8Xc0/SW2UOHipzYpVrx4Y7dSznh8ihaAFhmyCDaqqbHclFIzG7eF6q5QPzWikkCoYYRxDpP8 lHxiNQmEvhYTX6LhVj5aNVyBH51JZOTP8qequsk4R/c3VpViQ6JQ4SlCAI29nSMD9nuuanGI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-10_02,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 malwarescore=0 mlxscore=0 adultscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507100106 On 7/10/25 2:25 PM, Luca Weiss wrote: > On Thu Jul 10, 2025 at 2:10 PM CEST, Konrad Dybcio wrote: >> On 7/9/25 11:18 AM, Luca Weiss wrote: >>> As per the downstream devicetree for Milos, add a register write for >>> QCOM_USB_PHY_CFG_CTRL_1 as per the "eUSB2 HPG version 1.0.2 update". >>> >>> Reviewed-by: Neil Armstrong >>> Signed-off-by: Luca Weiss >>> --- >>> The downstream driver supports an arbitrary extra init sequence via >>> qcom,param-override-seq. >>> >>> volcano-usb.dtsi has the following which is implemented in this patch: >>> >>> /* eUSB2 HPG version 1.0.2 update */ >>> qcom,param-override-seq = >>> <0x00 0x58>; >>> --- >>> drivers/phy/phy-snps-eusb2.c | 6 ++++++ >>> 1 file changed, 6 insertions(+) >>> >>> diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2.c >>> index e232b8b4d29100b8fee9e913e2124788af09f2aa..87fc086424ba4d9fb3ce870aa7f7971a51d4a567 100644 >>> --- a/drivers/phy/phy-snps-eusb2.c >>> +++ b/drivers/phy/phy-snps-eusb2.c >>> @@ -420,6 +420,12 @@ static int qcom_snps_eusb2_hsphy_init(struct phy *p) >>> /* set default parameters */ >>> qcom_eusb2_default_parameters(phy); >>> >>> + if (of_device_is_compatible(p->dev.of_node, "qcom,milos-snps-eusb2-phy")) { >>> + /* eUSB2 HPG version 1.0.2 update */ >>> + writel_relaxed(0x0, phy->base + QCOM_USB_PHY_CFG_CTRL_1); >>> + readl_relaxed(phy->base + QCOM_USB_PHY_CFG_CTRL_1); >> >> Said HPG asks to clear bits [7:1] on all targets > > Okay, so make this unconditional and only update those bits instead of > writing the full register? Yes > > Keep the write at this location, or move the code somewhere else in the > function? Let's simply do this instead: diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2.c index 87f323e758d6..6c44d0366f34 100644 --- a/drivers/phy/phy-snps-eusb2.c +++ b/drivers/phy/phy-snps-eusb2.c @@ -392,7 +392,7 @@ static int qcom_snps_eusb2_hsphy_init(struct phy *p) snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_1, PHY_CFG_PLL_CPBIAS_CNTRL_MASK, - FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1)); + FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x0)); snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_4, PHY_CFG_PLL_INT_CNTRL_MASK Konrad