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Date: Wed, 30 Sep 2026 21:02:51 -0600 (MDT)
From: Paul Walmsley <pjw@kernel.org>
To: Yong-Xuan Wang <yongxuan.wang@sifive.com>
cc: Paul Walmsley <pjw@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, 
    Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alex@ghiti.fr>, 
    Samuel Holland <samuel.holland@sifive.com>, greentime.hu@sifive.com, 
    vincent.chen@sifive.com, zong.li@sifive.com, 
    linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] RISC-V: errata: Add SiFive MAL-9092 workaround
In-Reply-To: <20260817-sifive-errata-v1-1-6a80f1a2743d@sifive.com>
Message-ID: <a26672ca-adb7-a715-37d3-99da4a28403e@kernel.org>
References: <20260817-sifive-errata-v1-1-6a80f1a2743d@sifive.com>
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On Mon, 17 Aug 2026, Yong-Xuan Wang wrote:

> SiFive cores with MAL-9092 require fence.rw instructions around
> HLV/HLVX/HSV hypervisor instructions to ensure proper memory ordering
> when accessing guest memory.
> 
> Note that HSTATUS.HU is cleared during KVM initialization, restricting
> hypervisor instructions to HS-mode only. If future changes enable
> HSTATUS.HU for U-mode access, additional errata considerations will be
> needed.
> 
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>

Thanks, queued for v7.3-rc.


- Paul