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Mon, 26 Oct 2026 05:57:26 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c46bd6573dfsm316345866b.52.2026.10.26.05.57.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Oct 2026 05:57:24 -0700 (PDT) Message-ID: Date: Mon, 26 Oct 2026 13:57:21 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm6115: Add missing MDSS AHB clock To: Michael McAllister , Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rob Clark , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Adam Skladowski , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <7f99fda6f99d6053db240f2f1ba4d7b71da72261.1792852079.git.me@michaelmcallister.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <7f99fda6f99d6053db240f2f1ba4d7b71da72261.1792852079.git.me@michaelmcallister.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: qPwZZrrBhYyFuDTcxpBT4TwB8_AGafua X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI2MDA1MSBTYWx0ZWRfXwMqJ2Dm524X4 1EYdOyYXBL1hOBREXJGSB9AUkjk6hrsfStA9l3fdJKCreiCT4hMmjNIwPuP/e4pEVA23x3ngq/d IG0/HmnYPdW0rzyXpkXQf+V4vkAsTWsL0hhYYte5jXk6KumT0SXu7R7f65fJvtLREdUuTiMydKS tvpoMuxfEKT90ZV76CHmi5OYsYQ3zYIW4EisKdT+V1acCnDh+pVZUiyE5/9WLzkzZXKepzSGerC B4q5Hq259QuePEycRVnFm0ENpfi/emF68uJ734NwsznqrE3d8hzBCK3ua9Qm2VpGEyKHBgg9PM2 Du75PkQaMzoA4Lt+G2Et7pcGynI/dsPl8j+td1QcW0yA/mQabkUo9w4WARlrcq5+J1l1hOObZYL LBtG9PYFRb00Gti0udyJT9mWvpKJ8BLl3ULxgcZ13vL4xC/WYIGGVZn3XbTr9wvTlaDGrP0xYeQ NpcgjCBizXyobLJKc/w== X-Proofpoint-ORIG-GUID: qPwZZrrBhYyFuDTcxpBT4TwB8_AGafua X-Authority-Analysis: v=2.4 cv=K823jCWI c=1 sm=1 tr=0 ts=6adf4e38 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=VwQbUJbxAAAA:8 a=JwJ85b4fAAAA:8 a=EUspDBNiAAAA:8 a=FTenTJsohk8IYGkfYDAA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=qg2vb7sgHZQYDKbllo_a:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI2MDA1MSBTYWx0ZWRfXwqbfRdrRjNIO 2RzF12UveOD7PsBVQAlj56tJvljBzn+nK4asQjVettyzhHlGJuesI6Xa9ALL4zhJVNDjg0PaBYq tKE5Q/N854xHxtufbdaQAn51sQkonsE= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-26_02,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 spamscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610260051 On 10/24/26 4:27 PM, Michael McAllister wrote: > The MDSS node is missing DISP_CC_MDSS_AHB_CLK. Although the DPU child > already requests this clock, MDSS resumes before the child enables it. > The MDSS hardware-version register can then read as zero, causing > msm_mdss_enable() to skip UBWC configuration. > > On the Motorola Moto G10 (SM4250), this results in garbled compressed > scanout after display power cycling. Adding the clock restores the > UBWC configuration and makes compressed and linear scanout agree. > > Include the DISPCC AHB clock in the MDSS clock list so that its existing > bulk clock handling enables it before accessing the MDSS registers. > > Fixes: 705e50427d81 ("arm64: dts: qcom: sm6115: Add mdss/dpu node") > Cc: stable@vger.kernel.org > > Signed-off-by: Michael McAllister > --- Reviewed-by: Konrad Dybcio Konrad