From: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
To: Roger Quadros <rogerq@kernel.org>, tony@atomide.com
Cc: kishon@ti.com, nm@ti.com, vigneshr@ti.com,
linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>
Subject: Re: [PATCH 1/4] dt-bindings: memory-controllers: ti,gpmc: Add compatible for AM64
Date: Tue, 23 Nov 2021 20:47:57 +0100 [thread overview]
Message-ID: <a28532b1-bfa0-031b-91cc-070cad557599@canonical.com> (raw)
In-Reply-To: <20211123102607.13002-2-rogerq@kernel.org>
On 23/11/2021 11:26, Roger Quadros wrote:
> AM64 SoC contains the GPMC module. Add compatible for it.
>
> Newer SoCs don't necessarily map GPMC data region at the same place
> as legacy SoCs. Add reg-names "data", to provide this information to
> the device driver.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
> .../bindings/memory-controllers/ti,gpmc.yaml | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml
> index 25b42d68f9b3..1869cc6f949b 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml
> @@ -23,13 +23,20 @@ properties:
> items:
> - enum:
> - ti,am3352-gpmc
> + - ti,am64-gpmc
> - ti,omap2420-gpmc
> - ti,omap2430-gpmc
> - ti,omap3430-gpmc
> - ti,omap4430-gpmc
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: cfg
> + - const: data
I see your driver handles cases with only one reg item, but I have other
question - is it correct to have older (ARMv7) platform with two reg
items? Or can am64-gpmc come with only one reg?
IOW, I am surprised there is no if-else case precising this minItems
requirement for different SocS.
>
> interrupts:
> maxItems: 1
> @@ -44,6 +51,9 @@ properties:
> items:
> - const: fck
>
> + power-domains:
> + maxItems: 1
Similar, but looks like a weaker requirement - could an older SoC define
power-domain?
> +
> dmas:
> items:
> - description: DMA channel for GPMC NAND prefetch
>
Best regards,
Krzysztof
next prev parent reply other threads:[~2021-11-23 19:48 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-23 10:26 [PATCH 0/4] memory: omap-gpmc: Add AM64 SoC support Roger Quadros
2021-11-23 10:26 ` [PATCH 1/4] dt-bindings: memory-controllers: ti,gpmc: Add compatible for AM64 Roger Quadros
2021-11-23 19:47 ` Krzysztof Kozlowski [this message]
2021-11-25 12:18 ` Roger Quadros
2021-11-30 22:02 ` Rob Herring
2021-12-01 11:14 ` Roger Quadros
2021-11-23 10:26 ` [PATCH 2/4] memory: gpmc: Fix menuconfig visibility Roger Quadros
2021-11-23 10:27 ` Roger Quadros
2021-11-23 10:26 ` [PATCH 2/4] memory: omap-gpmc: " Roger Quadros
2021-11-23 19:43 ` Krzysztof Kozlowski
2021-11-25 12:09 ` Roger Quadros
2021-11-23 10:26 ` [PATCH 3/4] memory: omap-gpmc: Add support for GPMC on AM64 SoC Roger Quadros
2021-11-23 10:26 ` [PATCH 3/4] memory: omap-gpmc: " Roger Quadros
2021-11-23 10:28 ` Roger Quadros
2021-11-23 10:26 ` [PATCH 4/4] memory: omap-gpmc: check for nand node name instead of just compatibility Roger Quadros
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