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X-CSE-ConnectionGUID: 28IeSjOeQNCWBGE2qVZaIA== X-CSE-MsgGUID: lxmuGPFPRjqBAfg0/sQQvw== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="41685705" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="41685705" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Nov 2024 08:19:33 -0800 X-CSE-ConnectionGUID: rqykdkczQ828ldwGq4612g== X-CSE-MsgGUID: ChPcx99zRgCim36FNRxJvw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,260,1725346800"; d="scan'208";a="88587469" Received: from tfalcon-desk.amr.corp.intel.com (HELO [10.124.221.212]) ([10.124.221.212]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Nov 2024 08:19:32 -0800 Message-ID: Date: Tue, 5 Nov 2024 08:19:31 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] x86: cpu/bugs: add support for AMD ERAPS feature To: "Shah, Amit" , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-doc@vger.kernel.org" , "x86@kernel.org" Cc: "corbet@lwn.net" , "boris.ostrovsky@oracle.com" , "kai.huang@intel.com" , "pawan.kumar.gupta@linux.intel.com" , "jpoimboe@kernel.org" , "dave.hansen@linux.intel.com" , "daniel.sneddon@linux.intel.com" , "Lendacky, Thomas" , "seanjc@google.com" , "mingo@redhat.com" , "pbonzini@redhat.com" , "tglx@linutronix.de" , "Moger, Babu" , "Das1, Sandipan" , "hpa@zytor.com" , "peterz@infradead.org" , "bp@alien8.de" , "Kaplan, David" References: <20241031153925.36216-1-amit@kernel.org> <20241031153925.36216-2-amit@kernel.org> <05c12dec-3f39-4811-8e15-82cfd229b66a@intel.com> <4b23d73d450d284bbefc4f23d8a7f0798517e24e.camel@amd.com> <53c918b4-2e03-4f68-b3f3-d18f62d5805c@intel.com> <3ac6da4a8586014925057a413ce46407b9699fa9.camel@amd.com> <62063466-69bc-4eca-9f22-492c70b02250@intel.com> <975a74f19f9c8788e5abe99d37ca2b7697b55a23.camel@amd.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 11/5/24 02:39, Shah, Amit wrote: > On Mon, 2024-11-04 at 09:45 -0800, Dave Hansen wrote: > I'm expecting the APM update come out soon, but I have put together > > https://amitshah.net/2024/11/eraps-reduces-software-tax-for-hardware-bugs/ > > based on information I have. I think it's mostly consistent with what > I've said so far - with the exception of the mov-CR3 flush only > confirmed yesterday. That's better. But your original cover letter did say: Feature documented in AMD PPR 57238. which is technically true because the _bit_ is defined. But it's far, far from being sufficiently documented for Linux to actually use it. Could we please be more careful about these in the future? >> So, I'll flip this back around.  Today, X86_FEATURE_RSB_CTXSW zaps >> the >> RSB whenever RSP is updated to a new task stack.  Please convince me >> that ERAPS provides superior coverage or is unnecessary in all the >> possible combinations switching between: >> >> different thread, same mm > > This case is the same userspace process with valid addresses in the RSB > for that process. An invalid speculation isn't security sensitive, > just a misprediction that won't be retired. So we are good here. Does that match what the __switch_to_asm comment says, though? > /* > * When switching from a shallower to a deeper call stack > * the RSB may either underflow or use entries populated > * with userspace addresses. On CPUs where those concerns > * exist, overwrite the RSB with entries which capture > * speculative execution to prevent attack. > */ It is also talking just about call depth, not about same-address-space RSB entries being harmless. That's because this is also trying to avoid having the kernel consume any user-placed RSB entries, regardless of whether they're from the same mm or not. >> user=>kernel, same mm >> kernel=>user, same mm > > user-kernel is protected with SMEP. Also, we don't call > FILL_RETURN_BUFFER for these switches? Amit, I'm beginning to fear that you haven't gone and looked at the relevant code here. Please go look at SYM_FUNC_START(__switch_to_asm) in arch/x86/entry/entry_64.S. I believe this code is called for all task switches, including switching from a user task to a kernel task. I also believe that FILL_RETURN_BUFFER is used unconditionally for every __switch_to_asm call (when X86_FEATURE_RSB_CTXSW is on of course). Could we please start over on this patch? Let's get the ERAPS+TLB-flush nonsense out of the kernel and get the commit message right. Then let's go from there.