From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7415C2D0CE for ; Tue, 31 Dec 2019 06:21:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 86F55205ED for ; Tue, 31 Dec 2019 06:21:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="TOIJ/W/+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726673AbfLaGVr (ORCPT ); Tue, 31 Dec 2019 01:21:47 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:57534 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725536AbfLaGVr (ORCPT ); Tue, 31 Dec 2019 01:21:47 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBV6Lgj7126289; Tue, 31 Dec 2019 00:21:42 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1577773302; bh=QOzGlFMu3l6LM63W0dy0AcQj0m8XZ1pqTFVD+hNHXfI=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=TOIJ/W/+aTdOiiqBJbOZuTOazNwaPuepxu2Kg+0z0AFcniDqy9nMvlDtu44hd9OdF QOTaZF3XE+Yoa5JE7ypyXW2S8MX2YyUj6S7AqEMQsJi4UPYoGOVoNB06+TNxtYLc2Z uJ0SFxq4q54gIc3GGFf5GOYlZ28nJrZ3LTXuz/r4= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBV6LgHv046007 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 31 Dec 2019 00:21:42 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Tue, 31 Dec 2019 00:21:40 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Tue, 31 Dec 2019 00:21:40 -0600 Received: from [10.24.69.20] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBV6LcUj011774; Tue, 31 Dec 2019 00:21:39 -0600 Subject: Re: [PATCH v3 4/4] ARM: OMAP2+: sleep43xx: Call secure suspend/resume handlers To: "Andrew F. Davis" , Tony Lindgren CC: , References: <20191230185004.32279-1-afd@ti.com> <20191230185004.32279-5-afd@ti.com> From: Lokesh Vutla Message-ID: Date: Tue, 31 Dec 2019 11:50:47 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20191230185004.32279-5-afd@ti.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 31/12/19 12:20 AM, Andrew F. Davis wrote: > During suspend CPU context may be lost in both non-secure and secure CPU > states. The kernel can handle saving and restoring the non-secure context > but must call into the secure side to allow it to save any context it may > lose. Add these calls here. > > Note that on systems with OP-TEE available the suspend call is issued to > OP-TEE using the ARM SMCCC, but the resume call is always issued to the > ROM. This is because on waking from suspend the ROM is restored as the > secure monitor. It is this resume call that instructs the ROM to restore > OP-TEE, all subsequent calls will be handled by OP-TEE and should use the > ARM SMCCC. > > Signed-off-by: Andrew F. Davis > Acked-by: Dave Gerlach > --- > arch/arm/mach-omap2/omap-secure.h | 3 +++ > arch/arm/mach-omap2/pm33xx-core.c | 17 +++++++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h > index 736e594365f4..ba8c486c0454 100644 > --- a/arch/arm/mach-omap2/omap-secure.h > +++ b/arch/arm/mach-omap2/omap-secure.h > @@ -53,6 +53,9 @@ > #define OMAP4_PPA_L2_POR_INDEX 0x23 > #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 > > +#define AM43xx_PPA_SVC_PM_SUSPEND 0x71 > +#define AM43xx_PPA_SVC_PM_RESUME 0x72 > + > /* Secure RX-51 PPA (Primary Protected Application) APIs */ > #define RX51_PPA_HWRNG 29 > #define RX51_PPA_L2_INVAL 40 > diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c > index f11442ed3eff..4a564f676ff9 100644 > --- a/arch/arm/mach-omap2/pm33xx-core.c > +++ b/arch/arm/mach-omap2/pm33xx-core.c > @@ -28,6 +28,7 @@ > #include "prm33xx.h" > #include "soc.h" > #include "sram.h" > +#include "omap-secure.h" > > static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm; > static struct clockdomain *gfx_l4ls_clkdm; > @@ -166,6 +167,16 @@ static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), > { > int ret = 0; > > + /* Suspend secure side on HS devices */ > + if (omap_type() != OMAP2_DEVICE_TYPE_GP) { > + if (optee_available) > + omap_smccc_smc(AM43xx_PPA_SVC_PM_SUSPEND, 0); > + else > + omap_secure_dispatcher(AM43xx_PPA_SVC_PM_SUSPEND, > + FLAG_START_CRITICAL, > + 0, 0, 0, 0, 0); > + } > + > amx3_pre_suspend_common(); > scu_power_mode(scu_base, SCU_PM_POWEROFF); > ret = cpu_suspend(args, fn); > @@ -174,6 +185,12 @@ static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), > if (!am43xx_check_off_mode_enable()) > amx3_post_suspend_common(); > > + /* Resume secure side on HS devices */ > + if (omap_type() != OMAP2_DEVICE_TYPE_GP) > + omap_secure_dispatcher(AM43xx_PPA_SVC_PM_RESUME, > + FLAG_START_CRITICAL, > + 0, 0, 0, 0, 0); Don't you need to check optee_available here? Thanks and regards, Lokesh > + > return ret; > } > >