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Fri, 07 Feb 2025 07:25:17 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5177PFwb011606 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 07:25:15 GMT Received: from [10.239.133.114] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 6 Feb 2025 23:25:10 -0800 Message-ID: Date: Fri, 7 Feb 2025 15:25:08 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] coresight-tmc: stop disabling tmc when flush timeout To: Leo Yan CC: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , , , , References: <20250103-fix_cpu_hung-v1-1-a7b9b3893d44@quicinc.com> <20250206103213.GB8855@e132581.arm.com> Content-Language: en-US From: Yuanfang Zhang In-Reply-To: <20250206103213.GB8855@e132581.arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: tnsEgEBAKxKwCDPY-SvT6kd_vqoOjR6A X-Proofpoint-GUID: tnsEgEBAKxKwCDPY-SvT6kd_vqoOjR6A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_03,2025-02-07_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 mlxlogscore=999 mlxscore=0 adultscore=0 malwarescore=0 phishscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070056 On 2/6/2025 6:32 PM, Leo Yan wrote: > Hi Yuanfang, > > On Fri, Jan 03, 2025 at 04:01:54PM +0800, Yuanfang Zhang wrote: >> >> When multiple ETMs are enabled simultaneously, the time required >> to complete a flush in the process of reading the TMC device node >> may exceed the default wait time of 100us. > > Have you tried how long time would be safe to wait for the > TMCREADY_BIT bit to be set on your platform? yes, 400000us. > >> If the TMC capture is stopped while any ETM has not completed its >> flush, it can cause the corresponding CPU to hang. >> >> Fix the by checking the TMCReady bit after the flush. If TMCReady >> bit is set, TraceCaptEn bit can be clear; otherwise, return directly >> and stop the TMC read. > > When a timeout for TMC flush and stop is detected, if the driver > arbitrarily bails out without disabling TMC, this would leave the > hardware always on. > > I would like first know if a longer timeout can fix the issue. > > Thanks, > Leo > yes, longer timeout can fix this issue. >> Signed-off-by: Yuanfang Zhang >> --- >> drivers/hwtracing/coresight/coresight-tmc-etf.c | 17 +++++++++++++++-- >> drivers/hwtracing/coresight/coresight-tmc-etr.c | 22 +++++++++++++++++----- >> 2 files changed, 32 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c >> index d4f641cd9de69488fe3d1c1dc9b5a9eafb55ed59..bded290c42891d782344d9a6e63ebdbed6719133 100644 >> --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c >> +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c >> @@ -80,11 +80,21 @@ static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata) >> return; >> } >> >> -static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) >> +static int __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) >> { >> + int rc; >> + >> CS_UNLOCK(drvdata->base); >> >> tmc_flush_and_stop(drvdata); >> + >> + rc = tmc_wait_for_tmcready(drvdata); >> + if (rc) { >> + dev_err(&drvdata->csdev->dev, >> + "Failed to disable : TMC is not ready\n"); >> + CS_LOCK(drvdata->base); >> + return rc; >> + } >> /* >> * When operating in sysFS mode the content of the buffer needs to be >> * read before the TMC is disabled. >> @@ -94,6 +104,7 @@ static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) >> tmc_disable_hw(drvdata); >> >> CS_LOCK(drvdata->base); >> + return 0; >> } >> >> static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata) >> @@ -650,7 +661,9 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) >> ret = -EINVAL; >> goto out; >> } >> - __tmc_etb_disable_hw(drvdata); >> + ret = __tmc_etb_disable_hw(drvdata); >> + if (ret) >> + goto out; >> } >> >> drvdata->reading = true; >> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c >> index a48bb85d0e7f44a25b813f3c828cc3d705d16012..63a1f7501562fa0b5c2fe6ea53dce4d82842bec3 100644 >> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c >> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c >> @@ -1135,11 +1135,21 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata *drvdata) >> } >> } >> >> -static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata) >> +static int __tmc_etr_disable_hw(struct tmc_drvdata *drvdata) >> { >> + int rc; >> + >> CS_UNLOCK(drvdata->base); >> >> tmc_flush_and_stop(drvdata); >> + >> + rc = tmc_wait_for_tmcready(drvdata); >> + if (rc) { >> + dev_err(&drvdata->csdev->dev, >> + "Failed to disable : TMC is not ready\n"); >> + CS_LOCK(drvdata->base); >> + return rc; >> + } >> /* >> * When operating in sysFS mode the content of the buffer needs to be >> * read before the TMC is disabled. >> @@ -1150,7 +1160,7 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata) >> tmc_disable_hw(drvdata); >> >> CS_LOCK(drvdata->base); >> - >> + return 0; >> } >> >> void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) >> @@ -1779,9 +1789,11 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) >> } >> >> /* Disable the TMC if we are trying to read from a running session. */ >> - if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) >> - __tmc_etr_disable_hw(drvdata); >> - >> + if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) { >> + ret = __tmc_etr_disable_hw(drvdata); >> + if (ret) >> + goto out; >> + } >> drvdata->reading = true; >> out: >> spin_unlock_irqrestore(&drvdata->spinlock, flags); >> >> --- >> base-commit: fac04efc5c793dccbd07e2d59af9f90b7fc0dca4 >> change-id: 20250103-fix_cpu_hung-b5a95179ada4 >> >> Best regards, >> -- >> Yuanfang Zhang >> >>