From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751459AbdGZHIn (ORCPT ); Wed, 26 Jul 2017 03:08:43 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:59669 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750884AbdGZHIk (ORCPT ); Wed, 26 Jul 2017 03:08:40 -0400 Subject: Re: [PATCH v4 0/9] add support for Sama5d2 audio PLLs and enable ClassD To: Alexandre Belloni , Nicolas Ferre Cc: mark.rutland@arm.com, boris.brezillon@free-electrons.com, alsa-devel@alsa-project.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mturquette@baylibre.com, tiwai@suse.com, sboyd@codeaurora.org, lgirdwood@gmail.com, linux@armlinux.org.uk, robh+dt@kernel.org, broonie@kernel.org, cyrille.pitchen@wedev4u.fr, perex@perex.cz, thomas.petazzoni@free-electrons.com, linux-arm-kernel@lists.infradead.org References: <194d2fc6-4c88-bc3b-1127-b4c0bdb7c6a1@microchip.com> <20170726065732.zphp7zaug4ypcqzj@piout.net> From: Quentin Schulz Message-ID: Date: Wed, 26 Jul 2017 09:08:37 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170726065732.zphp7zaug4ypcqzj@piout.net> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Alexandre, On 26/07/2017 08:57, Alexandre Belloni wrote: > On 25/07/2017 at 17:44:19 +0200, Nicolas Ferre wrote: >> On 25/07/2017 at 09:37, Quentin Schulz wrote: >>> This patch series adds support for the audio PLLs and enables ClassD that >>> can be found in ATMEL Sama5d2 SoC. >>> >>> There are two audio PLLs (PMC and PAD) that shares the same parent (FRAC). >>> FRAC can output between 620 and 700MHz and only multiply the rate of its >>> parent. The two audio PLLs then divide the FRAC rate to best match the >>> asked rate. >>> >>> I basically took an old patch series posted by Nicolas on December, 6th >>> 2016[1][2][3] and the comments Boris did on the first version[4] Nicolas >>> sent on July, 15th 2015. >>> >>> I also fixed the function used to compute the divisors, removed useless >>> spinlocks and added a range to the audio frac PLL to stay within vendor's >>> supported range. Clocks that are children of gclk (generated-clk) are now >>> able to propagate rate to the audio PLL clocks when needed. >>> >>> However, there are multiple children clocks that could technically >>> change the rate of audio_pll (via gck). With the rate locking introduced >>> in Jerome Brunet's patch series[5], the first consumer to enable the clock >>> will be the one definitely setting the rate of the clock. Without the rate >>> locking, the last consumer to set the rate will be able to mess with the >>> rate. >>> Since audio IPs are most likely to request the same rate, we enforce >>> that the only clks able to modify gck rate are those of audio IPs. >>> >>> To remain consistent, we deny other clocks to be children of audio_pll. >> >> Quentin, >> >> Thanks for having revived this series. Everything's okay on my side for >> this v4. I think that my tag isn't missing from any patch of this >> series. Now we surely need to define which path it must take... >> > > I'll take the two dts patches now as the bindings have been acked. > Everything else should probably go through the clk tree. > Thanks for taking the dts patches. I agree that the remaining should go through the clk tree. @Stephen, @Michael, any objection (apart from your reviews on the patches) on taking this through your tree? Thanks, Quentin -- Quentin Schulz, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com