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([2a01:e0a:982:cbb0:8235:1ea0:1a75:c4d5]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfc8a4asm150018915e9.32.2025.02.10.07.30.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2025 07:30:02 -0800 (PST) Message-ID: Date: Mon, 10 Feb 2025 16:30:01 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8650: add PPI interrupt partitions for the ARM PMUs To: Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250207-topic-sm8650-pmu-ppi-partition-v1-0-dd3ba17b3eea@linaro.org> <20250207-topic-sm8650-pmu-ppi-partition-v1-2-dd3ba17b3eea@linaro.org> <6aa71142-3b1d-476f-9c78-1207fbbed3f5@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 10/02/2025 16:23, Konrad Dybcio wrote: > On 9.02.2025 3:44 PM, Neil Armstrong wrote: >> On 07/02/2025 21:30, Konrad Dybcio wrote: >>> On 7.02.2025 11:31 AM, Neil Armstrong wrote: >>>> The PMUs shares the same per-cpu (PPI) interrupt, so declare the proper >>>> interrupt partition maps and use the 4th interrupt cell to pass the >>>> partition phandle for each ARM PMU node. >>>> >>>> Signed-off-by: Neil Armstrong >>>> --- >>> >>>> @@ -5309,6 +5309,20 @@ intc: interrupt-controller@17100000 { >>>>               #size-cells = <2>; >>>>               ranges; >>>>   +            ppi-partitions { >>>> +                ppi_cluster0: interrupt-partition-0 { >>>> +                    affinity = <&cpu0 &cpu1>; >>>> +                }; >>>> + >>>> +                ppi_cluster1: interrupt-partition-1 { >>>> +                    affinity = <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>; >>>> +                }; >>>> + >>>> +                ppi_cluster2: interrupt-partition-2 { >>>> +                    affinity = <&cpu7>; >>>> +                }; >>> >>> I'm not sure this is accurate. >>> >>> I *think* it's cores 0-1 and 2-7, but I can't find a concrete answer >> >> Core 7 is a Cortex-X4, and has a dedicated PMU node, look at the cpu compatibles. > > Look at what these compatibles do in code. Nothing special for the X. So you suggest to revert Rob's change ? https://lore.kernel.org/all/20240417204247.3216703-1-robh@kernel.org/ So what I understood is that yes the code is the same, but the perf attributes are not necessarily the same between heterogeneous cores, so each instance here would load the attributes for each core type correctly instead of only using the ones from the first core Again, other SoCs uses this same scheme so I wonder what's the issue here ? Neil > > Konrad