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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-459ebede65asm220858905e9.8.2025.08.11.14.20.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Aug 2025 14:20:51 -0700 (PDT) Message-ID: Date: Mon, 11 Aug 2025 23:20:50 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/2] pwm: Add the S32G support in the Freescale FTM driver To: =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Frank.Li@nxp.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ghennadi.Procopciuc@nxp.com, s32@nxp.com References: <20250810185221.2767567-1-daniel.lezcano@linaro.org> <20250810185221.2767567-3-daniel.lezcano@linaro.org> <47ed1b83-9ace-475b-8279-6c7f394c35f3@linaro.org> Content-Language: en-US From: Daniel Lezcano In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 11/08/2025 23:11, Uwe Kleine-König wrote: > Hello Daniel, > > On Mon, Aug 11, 2025 at 11:44:32AM +0200, Daniel Lezcano wrote: >> On 11/08/2025 07:18, Uwe Kleine-König wrote: >>> All variants (up to now) have .has_fltctrl == .has_fltpol. Is there a >>> good reason that justifies two bools for the register description? >> >> Yeah, I agree it can be folded into a single has_flt_reg boolean. I can only >> guess that was done with the idea of sticking to the reference manual and >> perhaps having more variant to come with, eg., fltctrl=false and >> fltpol=true >> >> Do you want me to merge these boolean ? > > That's the obvious thing to do if you want the new variant supported :-) > > Unless you know that there is such a variant with .has_fltctrl != > .has_fltpol to appear soon, I prefer the simplified handling with only > one bool. > >>> Also I wonder about the fuss given that the two registers are not used >>> in the PWM driver. So this is only to prevent reading these registers >>> via regmap debug stuff? What happens if the memory locations are read >>> where the other implementations have these registers? >> >> The problem arises at resume time. >> >> /* restore all registers from cache */ >> clk_prepare(fpc->ipg_clk); >> regcache_cache_only(fpc->regmap, false); >> regcache_sync(fpc->regmap); >> >> Without skipping these registers, the kernel crashes on s32g2/3 > > That's a useful information for the commit log. Ok, thanks, I'll do the changes accordingly -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog