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Tue, 27 Oct 2026 04:31:02 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c46bd0f6f1asm441101766b.0.2026.10.27.04.30.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Oct 2026 04:31:00 -0700 (PDT) Message-ID: Date: Tue, 27 Oct 2026 12:30:57 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/5] drm/msm/a6xx: Program the PDC sequencer on Adreno 620 To: patches@brar.si, Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261027-adreno-a620-v4-0-b0095e028c76@brar.si> <20261027-adreno-a620-v4-2-b0095e028c76@brar.si> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261027-adreno-a620-v4-2-b0095e028c76@brar.si> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: 34uIbrQw9nNl6TMFY2HYlhIjZYdLSbzF X-Authority-Analysis: v=2.4 cv=Sfti5fRu c=1 sm=1 tr=0 ts=6ae08b78 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=27YcngequVK7hVtoIPYA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-GUID: 34uIbrQw9nNl6TMFY2HYlhIjZYdLSbzF X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI3MDA0NSBTYWx0ZWRfXxcGM/94pg1aX 0ctee0brU2gBUuxOGeSuu9uENKA8GTSibQEpmR7hP6RTo7YCzOmUt/ZhYmn1NvxQRKf5XORO5dy L/WVK7h9ZG05YXh62TvqYWmbp1M72jQ= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI3MDA0NSBTYWx0ZWRfXzZFFUscsPybj 383S2jbJdJ2RBxzbHqG8HltfLSE/5ueMBgVNET04sMzYAeAvdYM1qG+b0brLDI1uZFP9CcrCAdw 1U6XTzpCVxRHkPZWB0SD9nh/1+TqXUUzO72jOujzu4WJ169tKRvqyy3w6WSmjeHjGFxSyDGCDuz GplES5oCL07+Jy9ToA24b3ca2a9bFIuXUwtLsH6U5k17i4fOBUK+E8q61AXl1A9jMqZ7qlV5oaT ZJOV9ny5iuC+uSVPh3b2H5LykT4iWgab6SHdwDfssb9w9tJZkcNW0pxcxyu2ddw/cqIJHcsh3L8 5IIXDn/x2zA9BAEhGsYF6Qu2oJNNcDMj8JyRWJs/r3taCZEg1SGKbw8XAGmHUss6U3kT83wzRmQ mtzjWnGxgHF52/KApORBE8gGnzqaDFFxkJ/fntNV3dDjs0a87PfnTKMQ4a6jGv9eOiQbQMMR0V9 ZLWZqofymbLpZZ7cHGQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-27_02,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 clxscore=1015 adultscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610270045 On 10/27/26 8:14 AM, Ishu Brar via B4 Relay wrote: > From: Ishu Brar > > Unlike the rest of the A650 family, the A620 does not get its PDC set up > by AOP (the downstream devicetree has no pdc_in_aop for it). Without the > sequence, the RSC never acks the second power-up ("Unable to power on > the GPU RSC") and the device hangs. > > Program the sequence from the driver, taking the xo, mx and cx resource > addresses from cmd-db instead of the hardcoded ones. Like the downstream > driver, also program the VRM command when cmd-db has a vrm.soc resource. > Add adreno_is_a620() for the selection. > > Signed-off-by: Ishu Brar > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 35 +++++++++++++++++++++++++++------ > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > 2 files changed, 34 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 662f09bec9d5..8d426f1f127e 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -686,6 +686,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) > u32 seqmem0_drv0_reg = REG_A6XX_RSCC_SEQ_MEM_0_DRV0; > void __iomem *seqptr = NULL; > uint32_t pdc_address_offset; > + u32 mx_addr = 0x30010, cx_addr = 0x30000, vrm_addr = 0; We should grab these form cmd_db unconditionally, so: u32 cx_addr = cmd_db.. u32 mx_addr = cmd_db.. etc. > void __iomem *pdcptr; > bool pdc_in_aop = false; > > @@ -697,8 +698,18 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) > if (IS_ERR(pdcptr)) > return; > > - if (adreno_is_a650_family(adreno_gpu) || > - adreno_is_a7xx(adreno_gpu)) > + /* Unlike the rest of the A650 family, A620 has no PDC setup from AOP */ > + if (adreno_is_a620(adreno_gpu)) { > + pdc_address_offset = cmd_db_read_addr("xo.lvl"); > + mx_addr = cmd_db_read_addr("mx.lvl"); > + cx_addr = cmd_db_read_addr("cx.lvl"); > + vrm_addr = cmd_db_read_addr("vrm.soc"); but keep assigning vrm.addr here, as kgsl only ever writes there on A620, but the cmd_db lookup will succeed on other SoCs too Konrad