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Wed, 21 Oct 2026 03:02:59 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c4679ba8687sm59684266b.11.2026.10.21.03.02.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 03:02:58 -0700 (PDT) Message-ID: Date: Wed, 21 Oct 2026 12:02:56 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: mmcc-sdm660: enable the parent when pclk0_clk_src changes rate To: fabricioakio@gmail.com, Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Konrad Dybcio , AngeloGioacchino Del Regno , Martin Botka Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261002-sdm660-pclk0-parent-enable-v1-1-d6ff889144e4@gmail.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261002-sdm660-pclk0-parent-enable-v1-1-d6ff889144e4@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAzOSBTYWx0ZWRfX5DVCfnlo7QgP 32+C7Q74ITh067Ij1ttbvQ7O7vD0aAf5TSZp8ysZb+D3IKLYR8Y1BQFHFBWtHcweWUL4kb2Yn5Y 8lTXWN950N3UkAckRkOgQi+ZqZNOrKHWiUOSVf1z8Hm9NBSGeXDjH8+Ht5iNp1sKyGddOi66772 gdqQEgZqv4kyczjMDa4B5az3YPSTuTBocYFuR00kX2F6vekGc6EI9RZYr9Ze0BmEFIs8BWecdMS imqO7NpfM4iSoRFY0z5brY+MCYZjlyA07bto4Z1iCSNrSIMsykab3oE/MURZtrVsegN8WPMTquw MRsdUBXVV82DWFInpV7IVeK0RdV3V1rgjJU2XCHGJQzD9hSQ3BQnNdu6BYbvtBWdahgHYqRsWto RngJi36xwFBpP5t0ZeoZrqFgHIy/AQFh6ruNxsEDX5oLrzNZVoyAShx/r9xfpMJ3wDmgnjONROa nzoNIiuJuSBeJM0aFvw== X-Proofpoint-ORIG-GUID: MkjxgtcANvg5vWYiEE5KiAIunV3NfBGK X-Proofpoint-GUID: MkjxgtcANvg5vWYiEE5KiAIunV3NfBGK X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAzOSBTYWx0ZWRfX3g/HXwJPZxDt /LLjap5ucQC15KBAVEZUllbMUYlEmmhz2LJjuNkf4D+hOHYWahIXaC6s182SuYF3+jxuVXDIP2v w79KVlApzkKkWqxqqAPysBv77ltiU40= X-Authority-Analysis: v=2.4 cv=HL5WhYtv c=1 sm=1 tr=0 ts=6ad88dd4 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=BbLh709dquJP9IyRttkA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-21_02,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 impostorscore=0 clxscore=1015 phishscore=0 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210039 On 10/2/26 3:55 PM, Fabricio Akio via B4 Relay wrote: > From: Fabricio Akio > > pclk0_clk_src is fed by the DSI PHY PLL, which > dsi_pll_14nm_vco_set_rate() resets and only clk_prepare() restarts. The > DSI host sets the link rates before it prepares the PLL, so the RCG is > updated against a stopped source, and if it is enabled at that point > the update times out: > > pclk0_clk_src: rcg didn't update its configuration. > > Seen on a board whose simple-framebuffer node lists the pixel clock: > the RCG then reads enabled at msm's first modeset. > > Set CLK_OPS_PARENT_ENABLE so the core prepares the PLL around the rate > change, as dispcc-sm8250 does for its pixel clock sources since > commit acf7a91d0b0e ("clk: qcom: dispcc-sm8250: Enable parents for pixel > clocks"). > > Fixes: 5db3ae8b33de ("clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver") > Signed-off-by: Fabricio Akio > --- Reviewed-by: Konrad Dybcio Konrad