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([2001:b07:6468:f312:d80e:a78:c27b:93ed]) by smtp.gmail.com with ESMTPSA id t10sm58354wmi.1.2020.09.24.10.33.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Sep 2020 10:33:10 -0700 (PDT) Subject: Re: [PATCH v2 1/1] KVM: x86: fix MSR_IA32_TSC read for nested migration To: Maxim Levitsky , kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Jim Mattson , Wanpeng Li , Ingo Molnar , Sean Christopherson , Borislav Petkov , Thomas Gleixner , Vitaly Kuznetsov , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , Joerg Roedel , "H. Peter Anvin" References: <20200921103805.9102-1-mlevitsk@redhat.com> <20200921103805.9102-2-mlevitsk@redhat.com> From: Paolo Bonzini Message-ID: Date: Thu, 24 Sep 2020 19:33:09 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20200921103805.9102-2-mlevitsk@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21/09/20 12:38, Maxim Levitsky wrote: > MSR reads/writes should always access the L1 state, since the (nested) > hypervisor should intercept all the msrs it wants to adjust, and these > that it doesn't should be read by the guest as if the host had read it. > > However IA32_TSC is an exception. Even when not intercepted, guest still > reads the value + TSC offset. > The write however does not take any TSC offset into account. > > This is documented in Intel's SDM and seems also to happen on AMD as well. > > This creates a problem when userspace wants to read the IA32_TSC value and then > write it. (e.g for migration) > > In this case it reads L2 value but write is interpreted as an L1 value. > To fix this make the userspace initiated reads of IA32_TSC return L1 value > as well. > > Huge thanks to Dave Gilbert for helping me understand this very confusing > semantic of MSR writes. > > Signed-off-by: Maxim Levitsky > --- > arch/x86/kvm/x86.c | 16 ++++++++++++++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index 17f4995e80a7e..ed4314641360e 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -3219,9 +3219,21 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > case MSR_IA32_POWER_CTL: > msr_info->data = vcpu->arch.msr_ia32_power_ctl; > break; > - case MSR_IA32_TSC: > - msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; > + case MSR_IA32_TSC: { > + /* > + * Intel SDM states that MSR_IA32_TSC read adds the TSC offset > + * even when not intercepted. AMD manual doesn't explicitly > + * state this but appears to behave the same. > + * > + * However when userspace wants to read this MSR, we should > + * return it's real L1 value so that its restore will be correct. > + */ > + u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset : > + vcpu->arch.tsc_offset; > + > + msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset; > break; > + } > case MSR_MTRRcap: > case 0x200 ... 0x2ff: > return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); > Applied the patch as it is doing the sanest possible thing for the current semantics of host-initiated accesses. Paolo