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Tue, 09 Jun 2026 06:44:43 -0700 (PDT) X-Received: by 2002:a05:622a:ce:b0:50e:5cc3:6f59 with SMTP id d75a77b69052e-51795c0c10bmr185039121cf.5.1781012682479; Tue, 09 Jun 2026 06:44:42 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bf0553040a7sm1046373866b.50.2026.06.09.06.44.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Jun 2026 06:44:41 -0700 (PDT) Message-ID: Date: Tue, 9 Jun 2026 15:44:39 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] clk: qcom: add MSM8x60 MMCC driver To: Herman van Hazendonk , Bjorn Andersson , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org References: Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: ktD5K5ocr0ryhzBFGtdYTJpcX4Nu7O3k X-Authority-Analysis: v=2.4 cv=aa9RWxot c=1 sm=1 tr=0 ts=6a2818cc cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=cTwmTnRGAAAA:8 a=1-bfvCXmkCd3W1BBiQUA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 a=GUWCSGlMWfG-xDt5EnV5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA5MDEzMSBTYWx0ZWRfXw0N4hW2h4mdV A+L9HC1uDeI0TxgZOJ21ugSzy0dHvh8m+Ir1gGbnIWrhTbDhpnSZODSAkKTro/7n6VU7WkJjgc+ fhUbEf6kFg9nnoirDFX41O7tkCG+E0JS7lHABryQhP5Gj1asFsv3X2TOSFbTl4sMf/qMebBw4Fk DgO1Bon3SeEdaZD3WehvSoZ9ucfzN2IaoJXoYk6/BF9TggZYvx1pZvQxZDrxp16k7Hh3HmYWiio NJ6h/dv+R0AAAtKpKUNOh7Z5axYTNw/dYIOVqu9kwuQPY65RWMpxJwAQerb+dMbFqLjNNe7SHl4 PaGK+yMnOOS0YcrgoOTWw7DCyDnCa3I+4WJEX6ZF6xaOL/tgyOyYP/dnJeSpVHwfn0o+ju2VvTS e2eVTLKtCZhRCi2xP8yKQS3qScA8UkjYBYvnwfoq+xEVWhFYUkbHHojHZoiOPYKaY8mggKTavHB QLA1qbHzAF2FkAIPyLw== X-Proofpoint-ORIG-GUID: ktD5K5ocr0ryhzBFGtdYTJpcX4Nu7O3k X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-09_03,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 adultscore=0 spamscore=0 bulkscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606090131 On 5/30/26 3:58 PM, Herman van Hazendonk wrote: > Add a clock driver for the Multimedia Clock Controller (MMCC) on the > MSM8x60 family (MSM8260/MSM8660/APQ8060) - the Scorpion-class > generation that preceded MSM8960's Krait CPUs. > > The MMCC layout on MSM8x60 differs from MSM8960 in several ways that > make a separate driver cleaner than parameterising mmcc-msm8960.c: > > - the pix_rdi mux requires a custom set_parent op that temporarily > enables both parents during the glitch-free transition; > - the IJPEG GDSC requires releasing AXI, AHB and CORE resets; > - several rate-source pairs (MDP pixel, GFX2D/3D) only exist on > 8x60 (e.g. PLL2-derived 228571000/266667000 for graphics); > - the camera CSI / VFE / JPEG / VPE / ROT clock topology lacks the > later 8960 reorganisation. > > Used on the HP TouchPad (Tenderloin) for graphics (Adreno A220), > display (MDP4), camera (CSI/VFE), JPEG (Gemini), VIDC, VPE and > rotator. Reset IDs are exposed via a separate header so consumers > can reset the GDSCs and individual blocks. > > Signed-off-by: Herman van Hazendonk > --- [...] > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "pll2", > + .parent_data = (const struct clk_parent_data[]){ > + { .fw_name = "pxo", .name = "pxo_board" }, Please drop .name (the kernel-global clock lookup), this is only a backwards compatiblity measure on existing drivers. For new entries, .index is the best (because well, it's the fastest) [...] > +static struct clk_branch camclk0_clk = { > + .halt_reg = 0x01e8, > + .halt_bit = 15, > + /* > + * The legacy webOS kernel used halt_reg = NULL for this clock, > + * meaning it never checked the halt status. The hardware doesn't > + * properly report the clock state via the halt register. Use > + * BRANCH_HALT_SKIP to avoid the "status stuck at 'off'" warning. It may be that some piece of hw is holding this clock online behind the scenes. Is there perhaps a Qualcomm-authored commit that mentions the hw bug, or is it a guess? Due to the age of this chip I would imagine I won't be find an answer if you don't have one.. [...] I see you have a lot of inline note-to-self comments, please strip some of them. Konrad