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From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: AngeloGioacchino Del Regno 
	<angelogioacchino.delregno@collabora.com>,
	"mturquette@baylibre.com" <mturquette@baylibre.com>
Cc: "sboyd@kernel.org" <sboyd@kernel.org>,
	"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
	"wenst@chromium.org" <wenst@chromium.org>,
	"Miles Chen (陳民樺)" <Miles.Chen@mediatek.com>,
	"chun-jie.chen@mediatek.com" <chun-jie.chen@mediatek.com>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 2/2] clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parent
Date: Fri, 17 Jun 2022 18:10:42 +0800	[thread overview]
Message-ID: <a3c480a3aa87b87c707b92bc80040764d2434a03.camel@mediatek.com> (raw)
In-Reply-To: <20220617093424.75589-3-angelogioacchino.delregno@collabora.com>

On Fri, 2022-06-17 at 17:34 +0800, AngeloGioacchino Del Regno wrote:
> Like it was done for the vdo0_dp_intf0_dp_intf clock (used for eDP),
> add the CLK_SET_RATE_PARENT flag to CLK_VDO1_DPINTF (used for DP)
> and also fix its parent clock name as it has to be "top_dp" for two
> reasons:
>  - This is its real parent!
>  - Likewise to eDP/VDO0 counterpart, we need clock source
>    selection on CLK_TOP_DP.
> 
> Signed-off-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> Fixes: 269987505ba9 ("clk: mediatek: Add MT8195 vdosys1 clock
> support")
> 
Hello Angelo,

Thanks for this series.
I can use this series to do modetest using MT8195 Tomato Chromebook for
both dp and edp in kernel v5.19-rc1.

Therefore,
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
and,
Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>

BRs,
Bo-Chen


      reply	other threads:[~2022-06-17 10:10 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-17  9:34 [PATCH v2 0/2] MediaTek Kompanio 1200 MT8195 - DisplayPort clocks fixes AngeloGioacchino Del Regno
2022-06-17  9:34 ` [PATCH v2 1/2] clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parent AngeloGioacchino Del Regno
2022-06-17 10:10   ` Rex-BC Chen
2022-06-17  9:34 ` [PATCH v2 2/2] clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parent AngeloGioacchino Del Regno
2022-06-17 10:10   ` Rex-BC Chen [this message]

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