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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAzMDExMCBTYWx0ZWRfX7kI5B9bTFKv/ 9v5Fd7//Ltno04M1eKEOcZWg0ubmJWlHETbxoR9st0ntUJcoPCnJ7R2p/3ik/ZWsrxINO9cX/Oa 90LpVQr9kvp2Q9sYzaqRgVvzauOQg+gnyA7PCbm1ZcWfVjNUwxWyYu4YkcDxFPDF6Qov7kpLtKT VMzmQbrFt7CJPRWIqxC3scbZBtpkD8yh+cIl8hUdmKe2RBGKC2PeiGipqmE9UAQ4e2s9Yk0InDo H/H9UngvHgzuRRnI7diHYIWRj12RKT3N1XnAeONfiXI3JbEd38umxsWUB8PHj85KbG5I4Emn1aI VKZaEItoArhk/HnSBdwQDXwcWtfQ/LJOFNh05XaJ9ooCO7EHTniSPHbNIloolNB1EM7mkPz/qnH A8t9hRdRmo3tWVwroJuCyTgVoWbhB7pa3SLckUVa9hweKrAdBaKgEQ6yBse73L+pyVF+4ok05gs SM6XjzHuJHoDTXhgBMg== X-Proofpoint-ORIG-GUID: QyYrJyEzNRsKfXA61ke6QsL4R0aZy_KZ X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAzMDExMCBTYWx0ZWRfX1O94yfttRaaP eYsiM+vpOKCKb2w/CCSQJxnsgejPXzlGfxO0WWlQEIA0yS3co30GvWOKTWcbrKhx0dV5gzCyn+M zqDtMj4h8DdP6krW7PI38gNvbRiL5hY= X-Proofpoint-GUID: QyYrJyEzNRsKfXA61ke6QsL4R0aZy_KZ X-Authority-Analysis: v=2.4 cv=DMO/JSNb c=1 sm=1 tr=0 ts=6a996bc1 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=df3BZnECoes8ZJFSp-YA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-03_03,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 suspectscore=0 adultscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609030110 On 9/3/26 2:19 PM, Dmitry Baryshkov wrote: > DSI 6G v2.9 hosts (SM8650, SM8750, Kaanapali, etc.) reparent the byte and > pixel RCGs to the DSI PHY PLL at runtime from > dsi_link_clk_set_rate_6g_v2_9(), after the PHY has been enabled. However > dsi_calc_clk_rate_6g() runs earlier, in order to compute the bit clock > request for the PHY. At that point the byte RCG still has its reset > parent (XO), so clk_round_rate() returns a bogus rate, which then ends up > in the PHY bit clock request and the PLL gets programmed to a wrong > frequency, breaking the panel. > > Move the rounding to dsi_link_clk_set_rate_6g(), which is called after > the RCGs have been reparented to the PLL. Storing the rounded rate at > this point still makes later link_clk_set_rate() calls no-ops in the > CCF. Derive the byte interface clock rate from the rounded byte clock > rate, otherwise it would keep requesting the idealized rate and > retrigger the PLL on every transfer. > > Reported-by: Abel Vesa > Reported-by: Krzysztof Kozlowski > Fixes: 6cd33b6f4155 ("drm/msm/dsi: round 6G byte clock rate to the PLL-achievable value") > Assisted-by: LLM > Signed-off-by: Dmitry Baryshkov > --- I don't have HW to test it on hand, but it looks good to the eye: Reviewed-by: Konrad Dybcio Konrad