From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751223AbdKTNu0 (ORCPT ); Mon, 20 Nov 2017 08:50:26 -0500 Received: from mail-pg0-f65.google.com ([74.125.83.65]:35044 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751086AbdKTNuZ (ORCPT ); Mon, 20 Nov 2017 08:50:25 -0500 X-Google-Smtp-Source: AGs4zMZfe4bBkJgHJ+/viMPMq4S+BE3CibcziUGjUv0kMZKLYkbg+VxfYrPmicSA9n39bDnRcZ0Vfw== Subject: Re: [PATCH] drivers/perf: arm_pmu: save/restore cpu cycle counter in cpu_pm_pmu_notify To: Mark Rutland Cc: Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Lorenzo Pieralisi , Jia He References: <1510813648-45090-1-git-send-email-hejianet@gmail.com> <20171120123240.ohcdgv2nnoyrc7ov@lakrids.cambridge.arm.com> From: Jia He Message-ID: Date: Mon, 20 Nov 2017 21:50:15 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <20171120123240.ohcdgv2nnoyrc7ov@lakrids.cambridge.arm.com> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mark Thanks for your review. On 11/20/2017 8:32 PM, Mark Rutland Wrote: > Hi, > > On Thu, Nov 16, 2017 at 06:27:28AM +0000, Jia He wrote: >> Sometimes userspace need a high resolution cycle counter by reading >> pmccntr_el0. >> >> In commit da4e4f18afe0 ("drivers/perf: arm_pmu: implement CPU_PM >> notifier"), it resets all the counters even when the pmcr_el0.E and >> pmcntenset_el0.C are both 1 . That is incorrect. > I appreciate that you may wish to make use of the cycle counter from > userspace, but this is the intended behaviour kernel-side. Direct > userspace counter acceess is not supported. Sorry for my previous description. Not only user space, but also any pmccntr_el0 reading in kernel space is 0 except perf infrastructure. > > In power states where context is lost, any perf events are > saved/restored by cpu_pm_pmu_setup(). So we certainly shouldn't be > modifying the counter registers in any other PM code. > > We *could* expose counters to userspace on homogeneous systems, so long > as users stuck to the usual perf data page interface. However, this > comes with a number of subtle problems, and no-one's done the work to > enable this. > > Even then, perf may modify counters at any point in time, and > monotonicity (and/or presence) of counters is not guaranteed. Yes, the cycle counter register pmccntr_el0 will be impacted by perf usage.But do you think pmccntr_el0 is intented for perf only? Currently, many user space/kernel space programs will use pmccntr_el0 as a timestamp( just likethe rdtsc() on X86). After commit da4e4f18afe0, all the cycle counter readingis 0 because of CPU PM enter/exit state changes in armv8pmu_reset. -- Cheers, Jia