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Fri, 13 Dec 2024 10:19:50 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BDAJnfg008946 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Dec 2024 10:19:49 GMT Received: from [10.235.8.17] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 13 Dec 2024 02:19:43 -0800 Message-ID: Date: Fri, 13 Dec 2024 18:19:40 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 2/5] clk: qcom: Add CMN PLL clock controller driver for IPQ SoC To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , "Stephen Boyd" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , References: <20241107-qcom_ipq_cmnpll-v6-0-a5cfe09de485@quicinc.com> <20241107-qcom_ipq_cmnpll-v6-2-a5cfe09de485@quicinc.com> <7f0f2ad6-7895-46f8-8f80-0375dde2e763@oss.qualcomm.com> Content-Language: en-US From: Jie Luo In-Reply-To: <7f0f2ad6-7895-46f8-8f80-0375dde2e763@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _L0bXBXUc9Ftttnz-VjMHWv1-PTyJ-YZ X-Proofpoint-GUID: _L0bXBXUc9Ftttnz-VjMHWv1-PTyJ-YZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 clxscore=1015 malwarescore=0 adultscore=0 mlxlogscore=999 suspectscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412130070 On 12/13/2024 2:30 AM, Konrad Dybcio wrote: > On 7.11.2024 10:50 AM, Luo Jie wrote: >> The CMN PLL clock controller supplies clocks to the hardware >> blocks that together make up the Ethernet function on Qualcomm >> IPQ SoCs and to GCC. The driver is initially supported for >> IPQ9574 SoC. >> >> The CMN PLL clock controller expects a reference input clock >> from the on-board Wi-Fi block acting as clock source. The input >> reference clock needs to be configured to one of the supported >> clock rates. >> >> The controller supplies a number of fixed-rate output clocks. >> For the IPQ9574, there is one output clock of 353 MHZ to PPE >> (Packet Process Engine) hardware block, three 50 MHZ output >> clocks and an additional 25 MHZ output clock supplied to the >> connected Ethernet devices. The PLL also supplies a 24 MHZ >> clock as XO and a 32 KHZ sleep clock to GCC, and one 31.25 >> MHZ clock to PCS. >> >> Signed-off-by: Luo Jie >> --- > > [...] > >> + /* Enable PLL locked detect. */ >> + ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_CTRL, >> + CMN_PLL_CTRL_LOCK_DETECT_EN, >> + CMN_PLL_CTRL_LOCK_DETECT_EN); >> + if (ret) > > you can streamline these with regmap_set/clear_bits Ok, thanks, I will update to use it. > >> + return ret; >> + >> + /* >> + * Reset the CMN PLL block to ensure the updated configurations >> + * take effect. >> + */ >> + ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, >> + CMN_ANA_EN_SW_RSTN, 0); >> + if (ret) >> + return ret; >> + >> + usleep_range(1000, 1200); >> + ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, >> + CMN_ANA_EN_SW_RSTN, CMN_ANA_EN_SW_RSTN); >> + if (ret) >> + return ret; >> + >> + /* Stability check of CMN PLL output clocks. */ >> + return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val, >> + (val & CMN_PLL_CLKS_LOCKED), >> + 100, 100 * USEC_PER_MSEC); >> +} > > [...] > >> +static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) >> +{ >> + struct device *dev = &pdev->dev; >> + int ret; >> + >> + ret = devm_pm_runtime_enable(dev); >> + if (ret) >> + return ret; >> + >> + ret = devm_pm_clk_create(dev); >> + if (ret) >> + return ret; >> + >> + /* >> + * To access the CMN PLL registers, the GCC AHB & SYSY clocks > > SYS? > > Konrad Yes, I will correct it.