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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e894b60sm1919353666b.68.2025.01.03.04.29.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 03 Jan 2025 04:29:23 -0800 (PST) Message-ID: Date: Fri, 3 Jan 2025 13:29:20 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 2/5] clk: qcom: Add CMN PLL clock controller driver for IPQ SoC To: Luo Jie , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, quic_kkumarcs@quicinc.com, quic_suruchia@quicinc.com, quic_pavir@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, bartosz.golaszewski@linaro.org, srinivas.kandagatla@linaro.org References: <20250103-qcom_ipq_cmnpll-v8-0-c89fb4d4849d@quicinc.com> <20250103-qcom_ipq_cmnpll-v8-2-c89fb4d4849d@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250103-qcom_ipq_cmnpll-v8-2-c89fb4d4849d@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: SAlCcylwr5SoYaEnnarUyepvp-fdQ_cD X-Proofpoint-GUID: SAlCcylwr5SoYaEnnarUyepvp-fdQ_cD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 suspectscore=0 impostorscore=0 adultscore=0 mlxlogscore=999 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501030110 On 3.01.2025 8:31 AM, Luo Jie wrote: > The CMN PLL clock controller supplies clocks to the hardware > blocks that together make up the Ethernet function on Qualcomm > IPQ SoCs and to GCC. The driver is initially supported for > IPQ9574 SoC. > > The CMN PLL clock controller expects a reference input clock > from the on-board Wi-Fi block acting as clock source. The input > reference clock needs to be configured to one of the supported > clock rates. > > The controller supplies a number of fixed-rate output clocks. > For the IPQ9574, there is one output clock of 353 MHZ to PPE > (Packet Process Engine) hardware block, three 50 MHZ output > clocks and an additional 25 MHZ output clock supplied to the > connected Ethernet devices. The PLL also supplies a 24 MHZ > clock as XO and a 32 KHZ sleep clock to GCC, and one 31.25 > MHZ clock to PCS. > > Signed-off-by: Luo Jie > --- Acked-by: Konrad Dybcio Konrad