From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B12147DD7C for ; Thu, 4 Jun 2026 16:21:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590079; cv=none; b=l5lu4D1lzu4An/qmpCHLjRWHh1EDbqlvUIC87CDJStE6HSFycfpcbe1rgLEmZgsKaaLocY/0vYV+uTa5cSrIB4kmcM5ln87+Y+9cfFvKs6rDQwsKSRA2f3Lz69ytJceEeO6io5SsfHvJPnUuTn9kP6he450RRy4CfEwjm48V63U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590079; c=relaxed/simple; bh=Ol3GK2bhNyW7W2cSLGJsd4SLc+O/dkv6xNklq+RMDgA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jDh/mYjpYEGvoFcaTy/BJV0V/gRzhgBQj0ZMF7Y6YfzeqBCm40BKH3oEwxYfM6hMsjMwO6Kypw/r4Yn3TbJzgNE9DpjA3pVT6T+k7I+KSBW6SjZqib4teYB8iM5FqJm2Qf+fPnyR/cpVzQRxFTNDCCqHbbZA3ostejidu5wrllk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=iBVqW3qP; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="iBVqW3qP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780590078; x=1812126078; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ol3GK2bhNyW7W2cSLGJsd4SLc+O/dkv6xNklq+RMDgA=; b=iBVqW3qPQO04tM1be3jgpvnC7sRcOJzmNU46K3vuVjv0Luf+1fqLB8O5 866f9BMn8j9M2GmVT/ABPDKkGEdpAjC67mk+OILbCouLVwtGwg0o0x8NG mwe2QoCKi2/qgvvGuc66JAkRYCezcN7KGGnnJRi08trpBd+F5tWkIIGJu 0SXdfDfm2Ua4XtfMAueuw0mSC7yAoB1BOKQt7QNPIrYSk1ZVRzK9kfVAR Mk+1YAoHLVb5Mbzo5gb92ONjV/fpQ3WUf0MPTwSGnQiZVrhusIDq4puqy IbIcX4S8JfnJ5A50l0FkGA++vtb5ReQXWG0Yd/Bi1jwOxso2kpe2t6tcv w==; X-CSE-ConnectionGUID: 4FKulQR7Tqq+CvSbnDcJ/g== X-CSE-MsgGUID: z0c573dlRW+WcTOvCwIXOw== X-IronPort-AV: E=McAfee;i="6800,10657,11807"; a="92529108" X-IronPort-AV: E=Sophos;i="6.24,187,1774335600"; d="scan'208";a="92529108" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2026 09:21:18 -0700 X-CSE-ConnectionGUID: kC2B4T24TqS7216YQgUfjQ== X-CSE-MsgGUID: b+7sv1DRQnGPm5wl4o4GfA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,187,1774335600"; d="scan'208";a="248521047" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by orviesa003.jf.intel.com with ESMTP; 04 Jun 2026 09:21:14 -0700 From: Chen Yu To: tony.luck@intel.com, reinette.chatre@intel.com Cc: x86@kernel.org, linux-kernel@vger.kernel.org, bp@alien8.de, tglx@kernel.org, mingo@redhat.com, dave.hansen@linux.intel.com, hpa@zytor.com, dave.martin@arm.com, james.morse@arm.com, fenghuay@nvidia.com, babu.moger@amd.com, anil.keshavamurthy@broadcom.com Subject: [PATCH v2 3/6] x86/resctrl: Rename prev_msr to prev_mon_val Date: Fri, 5 Jun 2026 00:11:25 +0800 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Rename the prev_msr field in struct arch_mbm_state to prev_mon_val. With ERDT, the previous monitor value may come from an MMIO register rather than from an MSR, so the "msr" suffix is no longer accurate. The new name describes the field by its meaning (the previous monitor value) instead of by the access method. This is preparation for ERDT support, which reads monitoring counters via MMIO. No functional change. Co-developed-by: Anil S Keshavamurthy Signed-off-by: Anil S Keshavamurthy Signed-off-by: Chen Yu --- arch/x86/kernel/cpu/resctrl/internal.h | 8 +++---- arch/x86/kernel/cpu/resctrl/monitor.c | 30 +++++++++++++------------- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index 9c59bd5e028e..97065dc6e14f 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -31,13 +31,13 @@ /** * struct arch_mbm_state - values used to compute resctrl_arch_rmid_read()s * return value. - * @chunks: Total data moved (multiply by rdt_group.mon_scale to get bytes) - * @prev_msr: Value of IA32_QM_CTR last time it was read for the RMID used to - * find this struct. + * @chunks: Total data moved (multiply by rdt_group.mon_scale to get bytes) + * @prev_mon_val: Previous monitor counter value for the RMID used to + * find this struct. */ struct arch_mbm_state { u64 chunks; - u64 prev_msr; + u64 prev_mon_val; }; /* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */ diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index 9bd87bae4983..991f0a796551 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -186,7 +186,7 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_l3_mon_domain *d prmid = logical_rmid_to_physical_rmid(cpu, rmid); /* Record any initial, non-zero count value. */ - __rmid_read_phys(prmid, eventid, &am->prev_msr); + __rmid_read_phys(prmid, eventid, &am->prev_mon_val); } } @@ -209,16 +209,16 @@ void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_l3_mon_domai } } -static u64 mbm_overflow_count(u64 prev_msr, u64 cur_msr, unsigned int width) +static u64 mbm_overflow_count(u64 prev_val, u64 cur_val, unsigned int width) { u64 shift = 64 - width, chunks; - chunks = (cur_msr << shift) - (prev_msr << shift); + chunks = (cur_val << shift) - (prev_val << shift); return chunks >> shift; } static u64 get_corrected_val(struct rdt_resource *r, struct rdt_l3_mon_domain *d, - u32 rmid, enum resctrl_event_id eventid, u64 msr_val) + u32 rmid, enum resctrl_event_id eventid, u64 mon_val) { struct rdt_hw_l3_mon_domain *hw_dom = resctrl_to_arch_mon_dom(d); struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); @@ -227,12 +227,12 @@ static u64 get_corrected_val(struct rdt_resource *r, struct rdt_l3_mon_domain *d am = get_arch_mbm_state(hw_dom, rmid, eventid); if (am) { - am->chunks += mbm_overflow_count(am->prev_msr, msr_val, + am->chunks += mbm_overflow_count(am->prev_mon_val, mon_val, hw_res->mbm_width); chunks = get_corrected_mbm_count(rmid, am->chunks); - am->prev_msr = msr_val; + am->prev_mon_val = mon_val; } else { - chunks = msr_val; + chunks = mon_val; } return chunks * hw_res->mon_scale; @@ -245,7 +245,7 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *hdr, struct rdt_hw_l3_mon_domain *hw_dom; struct rdt_l3_mon_domain *d; struct arch_mbm_state *am; - u64 msr_val; + u64 mon_val; u32 prmid; int cpu; int ret; @@ -262,14 +262,14 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *hdr, hw_dom = resctrl_to_arch_mon_dom(d); cpu = cpumask_any(&hdr->cpu_mask); prmid = logical_rmid_to_physical_rmid(cpu, rmid); - ret = __rmid_read_phys(prmid, eventid, &msr_val); + ret = __rmid_read_phys(prmid, eventid, &mon_val); if (!ret) { - *val = get_corrected_val(r, d, rmid, eventid, msr_val); + *val = get_corrected_val(r, d, rmid, eventid, mon_val); } else if (ret == -EINVAL) { am = get_arch_mbm_state(hw_dom, rmid, eventid); if (am) - am->prev_msr = 0; + am->prev_mon_val = 0; } return ret; @@ -324,7 +324,7 @@ void resctrl_arch_reset_cntr(struct rdt_resource *r, struct rdt_l3_mon_domain *d memset(am, 0, sizeof(*am)); /* Record any initial, non-zero count value. */ - __cntr_id_read(cntr_id, &am->prev_msr); + __cntr_id_read(cntr_id, &am->prev_mon_val); } } @@ -332,14 +332,14 @@ int resctrl_arch_cntr_read(struct rdt_resource *r, struct rdt_l3_mon_domain *d, u32 unused, u32 rmid, int cntr_id, enum resctrl_event_id eventid, u64 *val) { - u64 msr_val; + u64 mon_val; int ret; - ret = __cntr_id_read(cntr_id, &msr_val); + ret = __cntr_id_read(cntr_id, &mon_val); if (ret) return ret; - *val = get_corrected_val(r, d, rmid, eventid, msr_val); + *val = get_corrected_val(r, d, rmid, eventid, mon_val); return 0; } -- 2.25.1