From: Mike Leach <mike.leach@arm.com>
To: Yingchao Deng <yingchao.deng@oss.qualcomm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
James Clark <james.clark@linaro.org>, Leo Yan <leo.yan@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, quic_yingdeng@quicinc.com,
tingwei.zhang@oss.qualcomm.com,
Jinlong Mao <jinlong.mao@oss.qualcomm.com>,
jie.gan@oss.qualcomm.com, nd@arm.com
Subject: Re: [PATCH v10 5/5] coresight: cti: document banked and missing base CTI sysfs registers
Date: Fri, 11 Sep 2026 10:06:47 +0100 [thread overview]
Message-ID: <a41ede73-b603-49e1-9443-af7ad11ba4b3@arm.com> (raw)
In-Reply-To: <20260615-extended_cti-v10-5-1c1694b6d8ed@oss.qualcomm.com>
Reviewed-by: Mike Leach <mike.leach@arm.com>
On 6/15/26 13:32, Yingchao Deng wrote:
> Document the new sysfs entries triginstatus[1-3], trigoutstatus[1-3],
> ittrigin[1-3], ittrigout[1-3], ittrigoutack[1-3] and ittriginack[1-3]
> in the coresight-cti ABI documentation.
>
> Also document the previously undocumented base integration test
> registers itctrl, itchin, itchinack, ittrigin, ittriginack, itchout,
> itchoutack, ittrigout and ittrigoutack, which were introduced in
> kernel version 5.7.
>
> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
> ---
> .../ABI/testing/sysfs-bus-coresight-devices-cti | 90 ++++++++++++++++++++++
> 1 file changed, 90 insertions(+)
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti
> index a2aef7f5a6d7..9d7831ac455b 100644
> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti
> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti
> @@ -128,12 +128,102 @@ KernelVersion: 5.7
> Contact: Mike Leach or Mathieu Poirier
> Description: (Read) read current status of input trigger signals
>
> +What: /sys/bus/coresight/devices/<cti-name>/regs/triginstatus[1-3]
> +Date: June 2026
> +KernelVersion: 7.3
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
> +Description: (Read) read current status of QCOM extended input trigger signals.
> +
> What: /sys/bus/coresight/devices/<cti-name>/regs/trigoutstatus
> Date: March 2020
> KernelVersion: 5.7
> Contact: Mike Leach or Mathieu Poirier
> Description: (Read) read current status of output trigger signals.
>
> +What: /sys/bus/coresight/devices/<cti-name>/regs/trigoutstatus[1-3]
> +Date: June 2026
> +KernelVersion: 7.3
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
> +Description: (Read) read current status of QCOM extended output trigger signals.
> +
> +What: /sys/bus/coresight/devices/<cti-name>/regs/itctrl
> +Date: March 2020
> +KernelVersion: 5.7
> +Contact: coresight@lists.linaro.org
> +Description: (RW) Control integration mode.
> +
> +What: /sys/bus/coresight/devices/<cti-name>/regs/itchin
> +Date: March 2020
> +KernelVersion: 5.7
> +Contact: coresight@lists.linaro.org
> +Description: (Read) Read the values of the CTCHIN inputs.
> +
> +What: /sys/bus/coresight/devices/<cti-name>/regs/itchinack
> +Date: March 2020
> +KernelVersion: 5.7
> +Contact: coresight@lists.linaro.org
> +Description: (Write) Write the value of the CTCHINACK input.
> +
> +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigin
> +Date: March 2020
> +KernelVersion: 5.7
> +Contact: coresight@lists.linaro.org
> +Description: (Read) Read the values of the CTTRIGIN inputs.
> +
> +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigin[1-3]
> +Date: June 2026
> +KernelVersion: 7.3
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
> +Description: (Read) Read the values of the QCOM extended CTTRIGIN inputs.
> +
> +What: /sys/bus/coresight/devices/<cti-name>/regs/ittriginack
> +Date: March 2020
> +KernelVersion: 5.7
> +Contact: coresight@lists.linaro.org
> +Description: (Write) Write the value of the CTTRIGINACK input.
> +
> +What: /sys/bus/coresight/devices/<cti-name>/regs/ittriginack[1-3]
> +Date: June 2026
> +KernelVersion: 7.3
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
> +Description: (Write) Write the value of the QCOM extended CTTRIGINACK input.
> +
> +What: /sys/bus/coresight/devices/<cti-name>/regs/itchout
> +Date: March 2020
> +KernelVersion: 5.7
> +Contact: coresight@lists.linaro.org
> +Description: (RW) Read or write the value of the CTCHOUT outputs.
> +
> +What: /sys/bus/coresight/devices/<cti-name>/regs/itchoutack
> +Date: March 2020
> +KernelVersion: 5.7
> +Contact: coresight@lists.linaro.org
> +Description: (Read) Read the value of the CTCHOUTACK input.
> +
> +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigout
> +Date: March 2020
> +KernelVersion: 5.7
> +Contact: coresight@lists.linaro.org
> +Description: (RW) Read or write the value of the CTTRIGOUT outputs.
> +
> +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigout[1-3]
> +Date: June 2026
> +KernelVersion: 7.3
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
> +Description: (RW) Read or write the value of the QCOM extended CTTRIGOUT outputs.
> +
> +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigoutack
> +Date: March 2020
> +KernelVersion: 5.7
> +Contact: coresight@lists.linaro.org
> +Description: (Read) Read the value of the CTTRIGOUTACK input.
> +
> +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigoutack[1-3]
> +Date: June 2026
> +KernelVersion: 7.3
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
> +Description: (Read) Read the value of the QCOM extended CTTRIGOUTACK input.
> +
> What: /sys/bus/coresight/devices/<cti-name>/channels/trigin_attach
> Date: March 2020
> KernelVersion: 5.7
>
next prev parent reply other threads:[~2026-09-11 9:07 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-15 12:32 [PATCH v10 0/5] Add Qualcomm extended CTI support Yingchao Deng
2026-06-15 12:32 ` [PATCH v10 1/5] coresight: cti: Convert trigger usage fields to dynamic Yingchao Deng
2026-09-11 9:08 ` Mike Leach
2026-06-15 12:32 ` [PATCH v10 2/5] coresight: cti: use __reg_addr() helper for register access Yingchao Deng
2026-06-15 12:32 ` [PATCH v10 3/5] coresight: cti: add Qualcomm extended CTI identification and quirks Yingchao Deng
2026-09-11 9:33 ` Mike Leach
2026-06-15 12:32 ` [PATCH v10 4/5] coresight: cti: expose banked sysfs registers for Qualcomm extended CTI Yingchao Deng
2026-06-15 12:32 ` [PATCH v10 5/5] coresight: cti: document banked and missing base CTI sysfs registers Yingchao Deng
2026-09-11 9:06 ` Mike Leach [this message]
2026-06-23 9:04 ` [PATCH v10 0/5] Add Qualcomm extended CTI support Leo Yan
2026-06-23 9:52 ` Yingchao Deng (Consultant)
2026-09-02 6:04 ` Jie Gan
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