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Fri, 21 Nov 2025 09:26:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IH56aTpsA3S0hWTXDgIt1z8Y3LX8eB9/2cGmDjNKQmmX/1ntjarn0bWDJ53np2JIBkBlsDUng== X-Received: by 2002:a05:6a00:2f08:b0:7bf:5011:d1e0 with SMTP id d2e1a72fcca58-7c58c4a7988mr2586414b3a.2.1763745998433; Fri, 21 Nov 2025 09:26:38 -0800 (PST) Received: from [192.168.0.195] ([49.204.24.237]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7c3f02423f6sm6634689b3a.39.2025.11.21.09.26.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Nov 2025 09:26:37 -0800 (PST) Message-ID: Date: Fri, 21 Nov 2025 22:56:32 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/6] clk: qcom: Add TCSR clock driver for Kaanapali To: Jingyi Wang , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251030-gcc_kaanapali-v2-v2-0-a774a587af6f@oss.qualcomm.com> <20251030-gcc_kaanapali-v2-v2-5-a774a587af6f@oss.qualcomm.com> <71e0d879-63ed-49e7-9bfe-c5cd8e0ca8ba@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <71e0d879-63ed-49e7-9bfe-c5cd8e0ca8ba@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: aaCumy0-KwUhWjJsEzh0hac_6ythh1aA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTIxMDEzMCBTYWx0ZWRfX2IvVT8fKDFFF fNtLZI0MMuqYmKKMoYx8P+m7LsRlqAVfCm6H7CdK304lReKwo0PFfx4h34XCWJXGL/X+qrKIbUw JezGtkAzw+4v6evvPsWvC608fP/8EIekNbPkbJxFsMWyoiymQQIsTJ5fNdjVf7dHn1syGfSvg2T G7PQT9rvGIJwGweBMcrXDdk2zjC0R2Qt24Rur4g0f5istUJucrT0M7ff0eWteh8HKHa3+nuEvYV 67umjW+BVbjQF/3lmF4ezCLCb2aQ9l1ritE80PPaJUh4VD/pKAyrns9bglC0xiF6yQ4RBggCZgh Mj4AzkmVhMn9TyFjpaPa4Q5wFpMSdTyLdR6ISsWElH9kPAFgC6P+cZ3KNx+ueTTZw0wvkPh3m7X iFl9UtybHSo9NIIxERPxFfzCzFnziw== X-Authority-Analysis: v=2.4 cv=bpdBxUai c=1 sm=1 tr=0 ts=6920a0d0 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=JNCjnJIMGS+pfmg2DM0HVg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=RaHAS9VqNI6p-X5hwAwA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: aaCumy0-KwUhWjJsEzh0hac_6ythh1aA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-21_05,2025-11-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511210130 On 11/18/2025 12:14 PM, Jingyi Wang wrote: >> + >> +static struct clk_branch tcsr_pcie_0_clkref_en = { >> + .halt_reg = 0x0, >> + .halt_check = BRANCH_HALT_DELAY, >> + .clkr = { >> + .enable_reg = 0x0, >> + .enable_mask = BIT(0), >> + .hw.init = &(const struct clk_init_data) { >> + .name = "tcsr_pcie_0_clkref_en", >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + > Hi Taniya, > > Here is a discussion for tcsr in this thread: > https://lore.kernel.org/all/01de9616-825b-4fbb-83cf- > e0bf91e8cf39@oss.qualcomm.com/ > > As TCSR_CLKS is a part of tcsr block, we should merge it as one node, the address > should be start at 0x01fc0000 instead of 0x01fd5044, so offset need to be added in the > tcsrcc reg configuration. > Yes, the next patch will incorporate the changes in offsets of the clocks and the device tree node needs to be updated. -- Thanks, Taniya Das