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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3eb07869655sm408646b6e.50.2024.12.05.11.01.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Dec 2024 11:01:53 -0800 (PST) Message-ID: Date: Thu, 5 Dec 2024 13:01:51 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] iio: adc: add Nuvoton NCT720x ADC driver From: David Lechner To: Eason Yang , avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, jic23@kernel.org, lars@metafoo.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nuno.sa@analog.com, javier.carrasco.cruz@gmail.com, andriy.shevchenko@linux.intel.com, marcelo.schmitt@analog.com, olivier.moysan@foss.st.com, mitrutzceclan@gmail.com, tgamblin@baylibre.com, matteomartelli3@gmail.com, alisadariana@gmail.com, gstols@baylibre.com, thomas.bonnefille@bootlin.com, ramona.nechita@analog.com, mike.looijmans@topic.nl, chanh@os.amperecomputing.com, KWLIU@nuvoton.com, yhyang2@nuvoton.com Cc: openbmc@lists.ozlabs.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241203091540.3695650-1-j2anfernee@gmail.com> <20241203091540.3695650-3-j2anfernee@gmail.com> <8f5ca298-54ba-4274-a35d-83be868fcfc8@baylibre.com> Content-Language: en-US In-Reply-To: <8f5ca298-54ba-4274-a35d-83be868fcfc8@baylibre.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 12/5/24 12:22 PM, David Lechner wrote: > On 12/3/24 3:15 AM, Eason Yang wrote: >> +static int nct720x_read_raw(struct iio_dev *indio_dev, >> + struct iio_chan_spec const *chan, >> + int *val, int *val2, long mask) >> +{ >> + int index = nct720x_chan_to_index[chan->address]; >> + u16 volt; >> + unsigned int value; >> + int err; >> + struct nct720x_chip_info *chip = iio_priv(indio_dev); >> + >> + if (chan->type != IIO_VOLTAGE) >> + return -EOPNOTSUPP; >> + >> + guard(mutex)(&chip->access_lock); >> + switch (mask) { >> + case IIO_CHAN_INFO_RAW: >> + err = regmap_read(chip->regmap16, REG_VIN[index], &value); >> + if (err < 0) >> + return err; >> + volt = (u16)value; >> + *val = volt >> 3; > > It seems strange that this is 13 bits when the chips are 8 and 12 bit. > >> + return IIO_VAL_INT; >> + case IIO_CHAN_INFO_SCALE: >> + /* From the datasheet, we have to multiply by 0.0004995 */ > > The scale is the same for both 8 bit and 12 bit chips? > >> + *val = 0; >> + *val2 = 499500; >> + return IIO_VAL_INT_PLUS_NANO; >> + default: >> + return -EINVAL; >> + } >> +} >> + Sorry, I got confused. The difference between the two chips is the number of channels, not the number of bits. Please ignore these two comments.