From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.mindbit.ro (xs1.mindbit.ro [80.86.107.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB09A175A99 for ; Mon, 17 Aug 2026 14:25:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.86.107.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786976735; cv=none; b=kiFujZJEPdv0LvoxShDUJ+VMf1CBm2CiCnJ0n8wuMjt40AAPRMeLQ2+67fbkEtFNBTsN+sO3qMoXNzPq+q2ig/YCXEx4/xjuATsSa5yzi7b6oPeWbxOE0a+1H3KodLJ1S+CVFfSG+lgOUlvhPtaFqbhVdNIF9C7S02O0S0zjGWI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786976735; c=relaxed/simple; bh=roywxzjwoDpRPpkuvJQWLXoKTdkrckRY7+MlEfFx5fw=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=joWeZSR/AROPf7gStOSRNbLUXR4u4EJt+EzWY54i4rzVwTbknX1OCcCqf9/YPRQt9Zi3FYmFvL/zqOt4iJwO7ETkB/6tCMO5+gUvWgs4sKHnENy4QsfKItX/450XguytLj0+2z8XaQPwkkLWsYpOkD+uLB3FqI2E12Ln6Jt0Mlw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=rendec.net; spf=pass smtp.mailfrom=rendec.net; dkim=pass (2048-bit key) header.d=rendec.net header.i=@rendec.net header.b=HXYXSPXW; arc=none smtp.client-ip=80.86.107.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=rendec.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rendec.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rendec.net header.i=@rendec.net header.b="HXYXSPXW" Received: from bat.kanata.rendec.net (unknown [72.143.213.121]) by mail.mindbit.ro (Postfix) with ESMTPSA id 18153C2DC3; Mon, 17 Aug 2026 17:25:24 +0300 (EEST) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.mindbit.ro 18153C2DC3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rendec.net; s=default; t=1786976730; bh=roywxzjwoDpRPpkuvJQWLXoKTdkrckRY7+MlEfFx5fw=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=HXYXSPXWdmUZu4Pue0ZKV6rZF2xLFPPHgLzx8gwJdilmCq6Tp+ba+iL91HpZbzsSO Uugtv6b6i37mHhwFp0pO0d+1wdyW/1I+Dp4AUvQYuyH1Ho4NKBvYbm6S1B/oHOsAno xjV7XLJduVv/cj4qpe+wYUli1z2MuF90D8fCFxtTozHvTk5P5/D8OFmK3t/8SksBCF YUa/+L5do1LbPE60fXDZ1t6TOVL5Sagd5Hnqfb8q6CBL7AbL6hwxMoQr5dMpBC2qoY Ax2FI2hPRu97+zp7E2igfoa+KTqSq6OmoA0ulTNy0pu5AQ+x2JpzT38wKzdW6KegvM Kdo+gwH/bjGsA== Message-ID: Subject: Re: [PATCH 5/5] irqchip/imsic: Use IPI_MAX instead of IMSIC_NR_IPI From: Radu Rendec To: Guo Ren Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, palmer@dabbelt.com, pjw@kernel.org, aou@eecs.berkeley.edu, alex@ghiti.fr, tglx@kernel.org, daniel.lezcano@kernel.org, anup@brainfault.org, hui.wang@canonical.com, samuel.holland@sifive.com Date: Mon, 17 Aug 2026 10:25:20 -0400 In-Reply-To: References: <20260816070049.2097442-1-guoren@kernel.org> <20260816070049.2097442-6-guoren@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.3 (3.58.3-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mon, 2026-08-17 at 21:05 +0800, Guo Ren wrote: > On Sun, Aug 16, 2026 at 11:28=E2=80=AFPM Radu Rendec wr= ote: > >=20 > > On Sun, 2026-08-16 at 07:00 +0000, Guo Ren wrote: > > > From: "GUO Ren (XuanTie)" > > >=20 > > > IMSIC was defining its own IMSIC_NR_IPI (=3D 8) which happened to mat= ch > > > the architecture's IPI_MAX. Now that IPI_MAX is exported from riscv > > > asm/smp.h, use the architecture constant and drop the private define. > > >=20 > > > This keeps the number of multiplexed IPIs in sync with the rest of th= e > > > RISC-V IPI infrastructure. > > >=20 > > > Signed-off-by: GUO Ren (XuanTie) > > > --- > > > =C2=A0drivers/irqchip/irq-riscv-imsic-early.c | 4 ++-- > > > =C2=A0drivers/irqchip/irq-riscv-imsic-state.h | 1 - > > > =C2=A02 files changed, 2 insertions(+), 3 deletions(-) > > >=20 > > > diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchi= p/irq-riscv-imsic-early.c > > > index 12efd241ce88..823f5f2ecb3d 100644 > > > --- a/drivers/irqchip/irq-riscv-imsic-early.c > > > +++ b/drivers/irqchip/irq-riscv-imsic-early.c > > > @@ -67,12 +67,12 @@ static int __init imsic_ipi_domain_init(void) > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 return 0; > > >=20 > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Create IMSIC IPI multiplexing */ > > > -=C2=A0=C2=A0=C2=A0=C2=A0 virq =3D ipi_mux_create(IMSIC_NR_IPI, imsic= _ipi_send); > > > +=C2=A0=C2=A0=C2=A0=C2=A0 virq =3D ipi_mux_create(IPI_MAX, imsic_ipi_= send); > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (virq <=3D 0) > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 return virq < 0 ? virq : -ENOMEM; > > >=20 > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Set vIRQ range */ > > > -=C2=A0=C2=A0=C2=A0=C2=A0 riscv_ipi_set_virq_range(virq, IMSIC_NR_IPI= ); > > > +=C2=A0=C2=A0=C2=A0=C2=A0 riscv_ipi_set_virq_range(virq, IPI_MAX); > > >=20 > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Announce that IMSIC is providing IP= Is */ > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pr_info("%pfwP: providing IPIs using i= nterrupt %d\n", imsic->fwnode, IMSIC_IPI_ID); > > > diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchi= p/irq-riscv-imsic-state.h > > > index c42ee180b305..878cc192ccec 100644 > > > --- a/drivers/irqchip/irq-riscv-imsic-state.h > > > +++ b/drivers/irqchip/irq-riscv-imsic-state.h > > > @@ -13,7 +13,6 @@ > > > =C2=A0#include > > >=20 > > > =C2=A0#define IMSIC_IPI_ID=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 1 > > > -#define IMSIC_NR_IPI=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 8 > > >=20 > > > =C2=A0struct imsic_vector { > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Fixed details of the vector */ > >=20 > > Reviewed-by: Radu Rendec >=20 > Thanks for the review, Radu. However, this patch depends on [1]. Would > you mind also reviewing [1]? >=20 > [1]: https://lore.kernel.org/linux-riscv/20260816070049.2097442-2-guoren@= kernel.org/ You're welcome! Sure, that makes sense, I reviewed [1] as well. --=20 Best regards, Radu