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Tue, 7 Jan 2020 20:16:39 +0000 Subject: Re: [PATCH v2] KVM: SVM: Override default MMIO mask if memory encryption is enabled To: Sean Christopherson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , Brijesh Singh References: <20200106224931.GB12879@linux.intel.com> <20200106233846.GC12879@linux.intel.com> From: Tom Lendacky Message-ID: Date: Tue, 7 Jan 2020 14:16:37 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 In-Reply-To: <20200106233846.GC12879@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SN6PR01CA0006.prod.exchangelabs.com (2603:10b6:805:b6::19) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 Received: from [10.236.30.74] (165.204.77.1) by SN6PR01CA0006.prod.exchangelabs.com (2603:10b6:805:b6::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2623.8 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: zMpvyS2xRvc1SOGTwolDzeL8T/g4PqcqR1+DvvKyx5ruqPG7WtD+E/I638xW606BmNxub88y0WqIDeGFug6jVutbkbj/+YwkGUBo9V7IrWeb6RlH/1P4bkb5P6dT07LhOa7IAkKhlQF3PQ3K//almIktCaI09C8c7a/+Vj3URrzIb7Vs+dt9Rr+oDSxA5okXF13uk4KjAUMjwhln+iwrk1ITQfvX990XQMUMRUzGWtLfJx2ho5yk1xAWwlv1knR9WzK7KHPfJbBwtm0WqbN8t8WX/pZsl+qAAtOj3i6Mja4cQSmDWBrJTukbjB+1c7FSQ4PmprqM4aX4dXLG/jjmXJgm7Kkv5EUBTpu0Ap5u+6SXoIp2pGo8PWne+O0j4P3Qxi4Zw1d0QfTeb5rpscQAHSkIXa3Rwi1ZRJ2mVb0Au8QE7PbLGqJjdn1qCJPNxPdU X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 27609db1-de51-4c75-11ef-08d793ae80ed X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2020 20:16:39.4626 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: qO7K0Fry01MG87+r8tSUSn5ZOaZOQBDGyCGzQOaEBepAf4JapITT5UNnhN+HdW6O7L+n7oW+nsxYdMbbut4Ncg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3355 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/6/20 5:38 PM, Sean Christopherson wrote: > On Mon, Jan 06, 2020 at 05:14:04PM -0600, Tom Lendacky wrote: >> On 1/6/20 4:49 PM, Sean Christopherson wrote: >>> This doesn't handle the case where x86_phys_bits _isn't_ reduced by SME/SEV >>> on a future processor, i.e. x86_phys_bits==52. >> >> Not sure I follow. If MSR_K8_SYSCFG_MEM_ENCRYPT is set then there will >> always be a reduction in physical addressing (so I'm told). > > Hmm, I'm going off APM Vol 2, which states, or at least strongly implies, > that reducing the PA space is optional. Section 7.10.2 is especially > clear on this: > > In implementations where the physical address size of the processor is > reduced when memory encryption features are enabled, software must > ensure it is executing from addresses where these upper physical address > bits are 0 prior to setting SYSCFG[MemEncryptionModEn]. It's probably not likely, but given what is stated, I can modify my patch to check for a x86_phys_bits == 52 and skip the call to set the mask, eg: if (msr & MSR_K8_SYSCFG_MEM_ENCRYPT && boot_cpu_data.x86_phys_bits < 52) { > > But, hopefully the other approach I have in mind actually works, as it's > significantly less special-case code and would naturally handle either > case, i.e. make this a moot point. I'll hold off on the above and wait for your patch. Thanks, Tom > > > Entry on SYSCFG: > > 3.2.1 System Configuration Register (SYSCFG) > > ... > > MemEncryptionMode. Bit 23. Setting this bit to 1 enables the SME and > SEV memory encryption features. > > The SME entry the above links to says: > > 7.10.1 Determining Support for Secure Memory Encryption > > ... > > Additionally, in some implementations, the physical address size of the > processor may be reduced when memory encryption features are enabled, for > example from 48 to 43 bits. In this case the upper physical address bits are > treated as reserved when the feature is enabled except where otherwise > indicated. When memory encryption is supported in an implementation, CPUID > Fn8000_001F[EBX] reports any physical address size reduction present. Bits > reserved in this mode are treated the same as other page table reserved bits, > and will generate a page fault if found to be non-zero when used for address > translation. > > ... > > 7.10.2 Enabling Memory Encryption Extensions > > Prior to using SME, memory encryption features must be enabled by setting > SYSCFG MSR bit 23 (MemEncryptionModEn) to 1. In implementations where the > physical address size of the processor is reduced when memory encryption > features are enabled, software must ensure it is executing from addresses where > these upper physical address bits are 0 prior to setting > SYSCFG[MemEncryptionModEn]. Memory encryption is then further controlled via > the page tables. >