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Miller" , linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: Nimesh Easow , Devaraj Rangasamy , Jens Wiklander , Ard Biesheuvel References: From: Gary R Hook Message-ID: Date: Thu, 19 Dec 2019 16:56:37 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SN2PR01CA0061.prod.exchangelabs.com (2603:10b6:800::29) To DM5PR12MB1449.namprd12.prod.outlook.com (2603:10b6:4:10::14) MIME-Version: 1.0 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: bd5433da-eae2-4466-dd3d-08d784d6b558 X-MS-TrafficTypeDiagnostic: DM5PR12MB2421:|DM5PR12MB2421: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:785; X-Forefront-PRVS: 0256C18696 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(366004)(39860400002)(396003)(346002)(376002)(136003)(189003)(199004)(31686004)(8936002)(81166006)(5660300002)(66946007)(86362001)(110136005)(54906003)(53546011)(186003)(478600001)(52116002)(26005)(81156014)(6506007)(8676002)(36756003)(316002)(4326008)(2616005)(66476007)(31696002)(2906002)(66556008)(6512007)(6486002);DIR:OUT;SFP:1101;SCL:1;SRVR:DM5PR12MB2421;H:DM5PR12MB1449.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UMHySeo/y0sDtA4WgFf9iTT8BvzKcU/eLbakSx9lFoNqszEuzVX9V/K+6iB8XeMtHndTSmOpAJhts7W4XbHpm+1B6iaZFcteAfDRqV81ngTpMGn751k/FFgEzBRCyUf770PLAR0xQMgFUsmoQenQjPJBKQKWDZrDL/bITxSl64kearerYFUTn+VXTSlzzMFPKd4mvwRIZ852DT5ISS3hTwQMnlabeXrzrVfR20NYMoTfoZIhl2BmnsFr2kQe5UUdqbNbmRiAtU7Pn9QTPDe94QlWAK/9YwcOd2N8Msz04ybfoG8jRG2PX0pG+giqNU37BQU8IpSUn/X+BQsY8i1pBhDTnP7kF9Bn1yG+k1cd/TeeuA0/p5/jyaEzdKP664T9l5+xwWVg/4tL8y/NT6ANAouiA5kOlKvl6E5mYW4gJyM2kJaIF6Jaz1VS10XQfmDX X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: bd5433da-eae2-4466-dd3d-08d784d6b558 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2019 22:56:39.8871 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: JvlPcdqZJqkbhagTqdxXUVcYw8LoU+Rqe/+71aYZ4eQ17Bq0JrGMUqdKHwoRkb3P X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2421 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/4/19 12:19 AM, Rijo Thomas wrote: > PSP can support both SEV and TEE interface. Therefore, move > SEV specific registers to a dedicated data structure. > TEE interface specific registers will be added in a later > patch. > > Cc: Ard Biesheuvel > Cc: Tom Lendacky > Cc: Jens Wiklander > Co-developed-by: Devaraj Rangasamy > Signed-off-by: Devaraj Rangasamy > Signed-off-by: Rijo Thomas Acked-by: Gary R Hook > --- > drivers/crypto/ccp/sev-dev.c | 17 ++++++++++++----- > drivers/crypto/ccp/sev-dev.h | 2 ++ > drivers/crypto/ccp/sp-dev.h | 6 +++++- > drivers/crypto/ccp/sp-pci.c | 16 ++++++++++++---- > 4 files changed, 31 insertions(+), 10 deletions(-) > > diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c > index a608b52..e68fa48 100644 > --- a/drivers/crypto/ccp/sev-dev.c > +++ b/drivers/crypto/ccp/sev-dev.c > @@ -65,7 +65,7 @@ static void sev_irq_handler(int irq, void *data, unsigned int status) > return; > > /* Check if it is SEV command completion: */ > - reg = ioread32(sev->io_regs + sev->psp->vdata->cmdresp_reg); > + reg = ioread32(sev->io_regs + sev->vdata->cmdresp_reg); > if (reg & PSP_CMDRESP_RESP) { > sev->int_rcvd = 1; > wake_up(&sev->int_queue); > @@ -82,7 +82,7 @@ static int sev_wait_cmd_ioc(struct sev_device *sev, > if (!ret) > return -ETIMEDOUT; > > - *reg = ioread32(sev->io_regs + sev->psp->vdata->cmdresp_reg); > + *reg = ioread32(sev->io_regs + sev->vdata->cmdresp_reg); > > return 0; > } > @@ -148,15 +148,15 @@ static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret) > print_hex_dump_debug("(in): ", DUMP_PREFIX_OFFSET, 16, 2, data, > sev_cmd_buffer_len(cmd), false); > > - iowrite32(phys_lsb, sev->io_regs + psp->vdata->cmdbuff_addr_lo_reg); > - iowrite32(phys_msb, sev->io_regs + psp->vdata->cmdbuff_addr_hi_reg); > + iowrite32(phys_lsb, sev->io_regs + sev->vdata->cmdbuff_addr_lo_reg); > + iowrite32(phys_msb, sev->io_regs + sev->vdata->cmdbuff_addr_hi_reg); > > sev->int_rcvd = 0; > > reg = cmd; > reg <<= SEV_CMDRESP_CMD_SHIFT; > reg |= SEV_CMDRESP_IOC; > - iowrite32(reg, sev->io_regs + psp->vdata->cmdresp_reg); > + iowrite32(reg, sev->io_regs + sev->vdata->cmdresp_reg); > > /* wait for command completion */ > ret = sev_wait_cmd_ioc(sev, ®, psp_timeout); > @@ -949,6 +949,13 @@ int sev_dev_init(struct psp_device *psp) > > sev->io_regs = psp->io_regs; > > + sev->vdata = (struct sev_vdata *)psp->vdata->sev; > + if (!sev->vdata) { > + ret = -ENODEV; > + dev_err(dev, "sev: missing driver data\n"); > + goto e_err; > + } > + > psp_set_sev_irq_handler(psp, sev_irq_handler, sev); > > ret = sev_misc_init(sev); > diff --git a/drivers/crypto/ccp/sev-dev.h b/drivers/crypto/ccp/sev-dev.h > index 3d84ac3..dd5c4fe 100644 > --- a/drivers/crypto/ccp/sev-dev.h > +++ b/drivers/crypto/ccp/sev-dev.h > @@ -40,6 +40,8 @@ struct sev_device { > > void __iomem *io_regs; > > + struct sev_vdata *vdata; > + > int state; > unsigned int int_rcvd; > wait_queue_head_t int_queue; > diff --git a/drivers/crypto/ccp/sp-dev.h b/drivers/crypto/ccp/sp-dev.h > index 53c1256..0394c75 100644 > --- a/drivers/crypto/ccp/sp-dev.h > +++ b/drivers/crypto/ccp/sp-dev.h > @@ -39,10 +39,14 @@ struct ccp_vdata { > const unsigned int rsamax; > }; > > -struct psp_vdata { > +struct sev_vdata { > const unsigned int cmdresp_reg; > const unsigned int cmdbuff_addr_lo_reg; > const unsigned int cmdbuff_addr_hi_reg; > +}; > + > +struct psp_vdata { > + const struct sev_vdata *sev; > const unsigned int feature_reg; > const unsigned int inten_reg; > const unsigned int intsts_reg; > diff --git a/drivers/crypto/ccp/sp-pci.c b/drivers/crypto/ccp/sp-pci.c > index b29d2e6..733693d 100644 > --- a/drivers/crypto/ccp/sp-pci.c > +++ b/drivers/crypto/ccp/sp-pci.c > @@ -262,19 +262,27 @@ static int sp_pci_resume(struct pci_dev *pdev) > #endif > > #ifdef CONFIG_CRYPTO_DEV_SP_PSP > -static const struct psp_vdata pspv1 = { > +static const struct sev_vdata sevv1 = { > .cmdresp_reg = 0x10580, > .cmdbuff_addr_lo_reg = 0x105e0, > .cmdbuff_addr_hi_reg = 0x105e4, > +}; > + > +static const struct sev_vdata sevv2 = { > + .cmdresp_reg = 0x10980, > + .cmdbuff_addr_lo_reg = 0x109e0, > + .cmdbuff_addr_hi_reg = 0x109e4, > +}; > + > +static const struct psp_vdata pspv1 = { > + .sev = &sevv1, > .feature_reg = 0x105fc, > .inten_reg = 0x10610, > .intsts_reg = 0x10614, > }; > > static const struct psp_vdata pspv2 = { > - .cmdresp_reg = 0x10980, > - .cmdbuff_addr_lo_reg = 0x109e0, > - .cmdbuff_addr_hi_reg = 0x109e4, > + .sev = &sevv2, > .feature_reg = 0x109fc, > .inten_reg = 0x10690, > .intsts_reg = 0x10694, >