From: "Bowman, Terry" <terry.bowman@amd.com>
To: Ankit Agrawal <ankita@nvidia.com>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: "dave@stgolabs.net" <dave@stgolabs.net>,
"jic23@kernel.org" <jic23@kernel.org>,
"dave.jiang@intel.com" <dave.jiang@intel.com>,
"alison.schofield@intel.com" <alison.schofield@intel.com>,
"vishal.l.verma@intel.com" <vishal.l.verma@intel.com>,
Jason Gunthorpe <jgg@nvidia.com>,
"aneesh.kumar@kernel.org" <aneesh.kumar@kernel.org>,
"aik@amd.com" <aik@amd.com>,
"yilun.xu@linux.intel.com" <yilun.xu@linux.intel.com>,
"iweiny@kernel.org" <iweiny@kernel.org>,
"ming.li@zohomail.com" <ming.li@zohomail.com>,
Richard Cheng <icheng@nvidia.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
Srirangan Madhavan <smadhavan@nvidia.com>,
"ilpo.jarvinen@linux.intel.com" <ilpo.jarvinen@linux.intel.com>,
"Smita.KoralahalliChannabasappa@amd.com"
<Smita.KoralahalliChannabasappa@amd.com>,
"andriy.shevchenko@linux.intel.com"
<andriy.shevchenko@linux.intel.com>,
"linux-coco@lists.linux.dev" <linux-coco@lists.linux.dev>
Subject: Re: [RFC PATCH 2/4] PCI/CXL: Populate and insert/remove pdev->coh_resource[]
Date: Thu, 22 Oct 2026 15:26:47 -0500 [thread overview]
Message-ID: <a51baa2d-1a2e-45f6-a862-d82b4b5a3f3e@amd.com> (raw)
In-Reply-To: <SAWPR12MB999267EF0CA5F3E284C1BC8A89B0672@SAWPR12MB999267.namprd12.prod.outlook.com>
On 10/20/2026 3:41 AM, Ankit Agrawal wrote:
>>> +
>>> + *res = DEFINE_RES_NAMED_DESC(config->hpa_range.start,
>>> + range_len(&config->hpa_range),
>>> + "CXL coherent memory",
>>> + IORESOURCE_MEM, IORES_DESC_NONE);
>>> +
>>
>> On platforms using Normalized Addressing the Endpoint decoders contain DPA ranges. This
>> patch will then record DPA ranges as a result. Translating this requires call to prm_cxl_dpa_spa() ?
>> The challenge is the PRM in drivers/cxl/core/atl.c may not be initialized this early.
>>
>
> Yeah, good point. On the platforms that I used, the HDM are precommitted
> and have HPA. But I agree, the snapshot must not silently record a DPA.
>
> Is there an existing way to tell at this point that the endpoint decoder is
> DPA-based? If yes, I intend to fail close with coh_resource[] left unpopulated
> Or would you prefer populating lazily until translations are available?
>
Hi Ankit,
For an example, normalized decoding is detected in core/atl.c:cxl_prm_setup_root(). Of course
this runs much later after cxl_core is loaded. Normalized decoder targets have the following at
the Endpoint HDM target entries:
(hpa_range.start == cxled->dpa_res->start)
-Terry
>
>>> + conflict = insert_resource_conflict(&iomem_resource, res);
>>> + if (conflict) {
>>> + pci_warn(pdev,
next prev parent reply other threads:[~2026-10-22 20:26 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-05 7:02 [RFC PATCH 0/4] PCI/TSM: Resolve TDISP coherent (CXL) ranges from precommitted HDM decoders Ankit Agrawal
2026-10-05 7:02 ` [RFC PATCH 1/4] PCI/TSM: Create MMIO descriptors via TDISP Report Ankit Agrawal
2026-10-05 11:17 ` Bradley Morgan
2026-10-14 14:01 ` Nikolay Borisov
2026-10-16 11:57 ` Xu Yilun
2026-10-16 12:35 ` Nikolay Borisov
2026-10-16 12:37 ` Xu Yilun
2026-10-20 8:19 ` Ankit Agrawal
2026-10-16 12:30 ` Xu Yilun
2026-10-05 7:02 ` [RFC PATCH 2/4] PCI/CXL: Populate and insert/remove pdev->coh_resource[] Ankit Agrawal
2026-10-07 19:27 ` Bowman, Terry
2026-10-20 8:41 ` Ankit Agrawal
2026-10-22 20:26 ` Bowman, Terry [this message]
2026-10-20 9:24 ` Richard Cheng
2026-10-20 9:37 ` Richard Cheng
2026-10-22 11:12 ` Ankit Agrawal
2026-10-05 7:02 ` [RFC PATCH 3/4] PCI/TSM: Derive the coherent-range IPA from CXL Ankit Agrawal
2026-10-06 16:13 ` Dave Jiang
2026-10-20 9:06 ` Ankit Agrawal
2026-10-12 19:21 ` Andy Shevchenko
2026-10-20 9:14 ` Ankit Agrawal
2026-10-20 9:30 ` Andy Shevchenko
2026-10-20 9:35 ` Ankit Agrawal
2026-10-05 7:02 ` [RFC PATCH 4/4] PCI/TSM: Support multiple coherent ranges via coh_idx Ankit Agrawal
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