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Thu, 30 Oct 2025 03:44:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE7ZUbP1cNloe4SPPg3Fub3BgyfPmfkn49K9yBfTrZy1O62kWKmDpe2ebpcLzeLbVJEXw4OTw== X-Received: by 2002:a05:6a21:2d05:b0:347:8414:da90 with SMTP id adf61e73a8af0-3478414dac4mr3238155637.0.1761821088211; Thu, 30 Oct 2025 03:44:48 -0700 (PDT) Received: from [10.217.217.147] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b7128885251sm16213400a12.17.2025.10.30.03.44.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Oct 2025 03:44:47 -0700 (PDT) Message-ID: Date: Thu, 30 Oct 2025 16:14:43 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts To: Dmitry Baryshkov Cc: Konrad Dybcio , Pankaj Patil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> <20250925-v3_glymur_introduction-v1-3-24b601bbecc0@oss.qualcomm.com> <2960a6fc-106b-4280-b4d4-9c1a3a449454@oss.qualcomm.com> <0a47016c-1d7e-4026-92bb-a13ac2ce169b@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDMwMDA4NyBTYWx0ZWRfX0TQqpPssGJY3 4pA0dWt+P6dSR8euST2kzbMm+QmI+UKEi1tNyDUSkLp+/7x+D+7+5rzCCm7B5Y6CEHeIZOk//lI N/uBzN85ubBRB1tO/KuywLOwOYpLIyhOrJdFFcmYS5jSZE6AG+nQfwea9sb1UNuHDgF+5yQZFKa AUny4zHmuafnp4h7ecw4myDThKSOGOYe35vcQAByOUkgqB72PvIDccf+ueCxpRiFcRMGBE9cKch x0cznIHAf8dJLAS91ZiyfN6qHDmTtrVFBBx7WlBq6gsD8I3LAGBHHXBj3z9ELqxy+XHyw62g6a+ SB0yc9AQSG15fCpuSueilFZxTpPh2Vqp/aMNqFtnpR8Fl7qqveKLWhn4PwpK74mBSjVk+CUDgOu aT8SjWaLvmzPTeD1QLWv2Y+acNTyVg== X-Proofpoint-ORIG-GUID: flLwq6HcDBdcwuX3Fueu3BN2Q_Hb8kBM X-Authority-Analysis: v=2.4 cv=LoWfC3dc c=1 sm=1 tr=0 ts=690341a1 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z2WFzCv5d8wuYGPiYnEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-GUID: flLwq6HcDBdcwuX3Fueu3BN2Q_Hb8kBM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-30_03,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510300087 On 10/29/2025 4:06 PM, Dmitry Baryshkov wrote: > On Wed, Oct 29, 2025 at 03:30:54PM +0530, Taniya Das wrote: >> >> >> On 9/25/2025 3:46 PM, Konrad Dybcio wrote: >>>> + tcsrcc: clock-controller@1fd5044 { >>>> + compatible = "qcom,glymur-tcsr"; >>>> + reg = <0x0 0x1fd5044 0x0 0x48>; >>> We can map 0x1fd5000 - 0x1fd5094 inclusive, as that seems like a >>> logical subblock (this would require adjusting the driver) >>> >> >> Konrad, we encountered issues when trying to map regions beyond just the >> clock reference registers. Normally, we map the entire address range of >> a clock controller (CC) module in the device tree. However, for TCSRCC >> where CLKREF_EN registers are located within shared modules like TCSR or >> TLMM—we don't own the whole address space, and mapping the full range >> can overlap with other devices. >> To avoid this, we propose defining the base address as the first >> register actually used, and the size to only include up to the last >> register we use. This ensures we only map the relevant subblock, >> preventing conflicts with other device nodes. > > Then you need to behave slightly differently: map the full range at the > basic device (TLMM, TCSR, etc.) and then create TCSRCC as a child device > to that node (and use paren't regmap to access the registers). > Dmitry, I agree that this approach is ideal. However, the current hardware implementation isn’t consistent across multiple SoCs, which means the driver design also needs to adapt. Given these differences, we decided to strictly map only the range of hardware registers that are actually used for clocks, rather than the entire module. >> >> So want to keep the mapping same from the start of clockref clocks. >> >>> There's also a laaaarge pool of various TCSR_ registers between >>> the previous node and this one.. but we can leave that in case we >>> need to describe it in a specific way some day >>>> + #clock-cells = <1>; >>>> + #reset-cells = <1>; >>>> + }; >>>> + >> >> -- >> Thanks, >> Taniya Das >> > -- Thanks, Taniya Das