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X-CSE-ConnectionGUID: lyg7I62fRx6FxjrbsgrZtQ== X-CSE-MsgGUID: jN9Nndj4TcKK0CxP/5np4A== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="80278687" X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="80278687" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 18:30:37 -0700 X-CSE-ConnectionGUID: 4htR46KDQemo9GoYg73Emg== X-CSE-MsgGUID: qlvqxnXMRbGvxt7XONg2cQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="282184505" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.241.147]) ([10.124.241.147]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 18:30:35 -0700 Message-ID: Date: Wed, 3 Jun 2026 09:30:31 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 5/8] perf/x86/intel/uncore: Factor out box setup code To: Zide Chen , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org References: <20260601170114.173359-1-zide.chen@intel.com> <20260601170114.173359-6-zide.chen@intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20260601170114.173359-6-zide.chen@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Reviewed-by: Dapeng Mi On 6/2/2026 1:01 AM, Zide Chen wrote: > The PCI uncore PMU path already implements a lazy registration model: > the PMU is registered when the first active box appears and > unregistered when the last active box is removed. > > Factor this registration management into a shared helper, so the same > code can be reused by the MSR and MMIO paths in later changes. > > No functional change intended. > > Reviewed-by: Ian Rogers > Signed-off-by: Zide Chen > --- > arch/x86/events/intel/uncore.c | 40 ++++++++++++++++++++++++---------- > 1 file changed, 28 insertions(+), 12 deletions(-) > > diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c > index 6df44f69cc5b..283e41933ba7 100644 > --- a/arch/x86/events/intel/uncore.c > +++ b/arch/x86/events/intel/uncore.c > @@ -1148,6 +1148,29 @@ uncore_pci_find_dev_pmu(struct pci_dev *pdev, const struct pci_device_id *ids) > return pmu; > } > > +static int uncore_box_setup(struct intel_uncore_pmu *pmu, > + struct intel_uncore_box *box) > +{ > + int ret; > + > + uncore_box_init(box); > + > + /* First active box registers the pmu. */ > + if (atomic_inc_return(&pmu->activeboxes) > 1) > + return 0; > + > + ret = uncore_pmu_register(pmu); > + if (ret) { > + atomic_dec(&pmu->activeboxes); > + goto err; > + } > + > + return 0; > +err: > + uncore_box_exit(box); > + return ret; > +} > + > /* > * Register the PMU for a PCI device > * @pdev: The PCI device. > @@ -1173,20 +1196,13 @@ static int uncore_pci_pmu_register(struct pci_dev *pdev, > box->dieid = die; > box->pci_dev = pdev; > box->pmu = pmu; > - uncore_box_init(box); > > - pmu->boxes[die] = box; > - if (atomic_inc_return(&pmu->activeboxes) > 1) > - return 0; > - > - /* First active box registers the pmu */ > - ret = uncore_pmu_register(pmu); > - if (ret) { > - atomic_dec(&pmu->activeboxes); > - pmu->boxes[die] = NULL; > - uncore_box_exit(box); > + ret = uncore_box_setup(pmu, box); > + if (!ret) > + pmu->boxes[die] = box; > + else > kfree(box); > - } > + > return ret; > } >