From: Neil Leeder <nleeder@codeaurora.org>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Mark Langsdorf <mlangsdo@redhat.com>,
Mark Salter <msalter@redhat.com>, Jon Masters <jcm@redhat.com>,
Timur Tabi <timur@codeaurora.org>,
cov@codeaurora.org, nleeder@codeaurora.org
Subject: Re: [PATCH v4 2/2] soc: qcom: add l2 cache perf events driver
Date: Fri, 16 Sep 2016 15:51:58 -0400 [thread overview]
Message-ID: <a53b1786-c859-5d44-f2b9-1607d9b472b3@codeaurora.org> (raw)
In-Reply-To: <20160916164011.GB3179@leverpostej>
On 9/16/2016 12:40 PM, Mark Rutland wrote:
> On Fri, Sep 16, 2016 at 11:33:39AM -0400, Neil Leeder wrote:
[...]
>> On 9/1/2016 12:30 PM, Mark Rutland wrote:
>>> On Tue, Aug 30, 2016 at 01:01:33PM -0400, Neil Leeder wrote:
>>>> + /* Don't allow groups with mixed PMUs, except for s/w events */
>>>> + if (event->group_leader->pmu != event->pmu &&
>>>> + !is_software_event(event->group_leader)) {
>>>> + dev_warn(&l2cache_pmu->pdev->dev,
>>>> + "Can't create mixed PMU group\n");
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + list_for_each_entry(sibling, &event->group_leader->sibling_list,
>>>> + group_entry)
>>>> + if (sibling->pmu != event->pmu &&
>>>> + !is_software_event(sibling)) {
>>>> + dev_warn(&l2cache_pmu->pdev->dev,
>>>> + "Can't create mixed PMU group\n");
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + hwc->idx = -1;
>>>> + hwc->config_base = event->attr.config;
>>>> +
>>>> + /*
>>>> + * Ensure all events are on the same cpu so all events are in the
>>>> + * same cpu context, to avoid races on pmu_enable etc.
>>>> + */
>>>> + slice = get_hml2_pmu(event->cpu);
>>>> + event->cpu = slice->on_cpu;
>>>
>>> This could put an event on a different CPU to its group siblings, which
>>> is broken.
>>
>> This is the same logic as in arm-ccn.c:arm_ccn_pmu_event_init(), where there
>> is a single CPU designated as the CPU to be used for all events.
>>
>> All events for this slice are forced to slice->on_cpu which is the CPU
>> set in the cpumask for this slice.
>
> The CCN is a little different. For the CCN, a single CPU is designated
> to handle *all* events.
>
> For this driver, a CPU is designated per-slice, judging by the existence
> of hml2_pmu::on_cpu (unless that's superfluous). We've only verified
> that the events are all for this PMU, not the same slice, and thus each
> event->cpu may differ.
>
I see. So I can add a check that the group_leader event must be on the
same slice, and thus on the same CPU.
>> I'm not sure how this can put an event on a different CPU to its group
>> siblings?
>
> In practice today, we'll try to schedule the event on it's group
> leader's CPU, but accounting and subsequent manipulation could go wrong.
>
> Thanks,
> Mark.
>
Neil
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.
prev parent reply other threads:[~2016-09-16 19:52 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-30 17:01 [PATCH v4 0/2] " Neil Leeder
2016-08-30 17:01 ` [PATCH v4 1/2] soc: qcom: provide mechanism for drivers to access L2 registers Neil Leeder
2016-08-30 17:01 ` [PATCH v4 2/2] soc: qcom: add l2 cache perf events driver Neil Leeder
2016-09-01 16:30 ` Mark Rutland
2016-09-02 10:06 ` Mark Rutland
2016-09-16 15:33 ` Neil Leeder
2016-09-16 16:40 ` Mark Rutland
2016-09-16 19:51 ` Neil Leeder [this message]
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